ARIES v3.0
© March, 2023 Centre for Development of Advanced Computing (C-DAC)
Page | 10/12
SL
NO.
SPECIFICATIONS
THEJAS 32
ARIES BOARD
REMARKS
1
SPI (4)
SPI0_SS
J1_8
Connected to HEADER J1
2
SPI0_SCLK
J1_5
3
SPI0_MISO
J1_6
4
SPI0_MOSI
J1_7
5
SPI1_SS
J7_6
Connected to HEADER J7
6
SPI1_SCLK
J7_4
7
SPI1_MISO
J7_2
8
SPI1_MOSI
J7_3
9
SPI2_SS
J4_6
Connected to HEADER J4
10
SPI2_SCLK
J4_4
11
SPI2_MISO
J4_2
12
SPI2_MOSI
J4_3
13
SPI3_SS
U5_1
Connected to SPI BOOT FLASH IC
14
SPI3_SCLK
U5_6
15
SPI3_MISO
U5_2
16
SPI3_MOSI
U5_5
17
I2C (3)
SCL
J10_12
Connected to HEADER J10
18
SDA
J10_10
19
SCL_1
J1_1
Connected to HEADER J1
20
SDA_1
J1_2
21
SCL_2
U9_10
Connected to I2C ADC IC
22
SDA_2
U9_9
23
UART (3)
UART0_RXD
U10_18
Connected to UART TO USB
INTERFACE IC
24
UART0_TXD
U10_17
25
UART1_RX
J2_15
Connected to HEADER J2
26
UART1_TX
J2_13
27
UART2_RX
J5_1
Connected to HEADER J5
28
UART2_TX
J5_2
29
PWM (8)
PWM[0]
J2_5
Connected to HEADER J2
30
PWM[1]
J2_3
31
PWM[2]
J2_1
32
PWM[3]
J1_10
Connected to HEADER J1
33
PWM[4]
J1_9
34
PWM[5]
J3_3
Connected to HEADER J3
35
PWM[6]
J3_2
36
PWM[7]
J3_1
37
GPIO (32)
GPIO0
J2_11
Connected to HEADER J2
38
GPIO1
J2_9
39
GPIO2
J2_7
40
GPIO3
J2_16
41
GPIO4
J2_14
42
GPIO5
J2_12
