NINA-W1 series - System integration manual
UBX-17005730 - R15
System description
Page 10 of 54
C1 - Public
If decoupling capacitors are needed on the supply rails, it is best practice to position these as close as
possible to the NINA-W1 series module. The power routing of some host system designs makes
decoupling capacitance unnecessary.
For electrical specifications, refer to the appropriate NINA-W1 series data sheet [2] [3] [4].
1.6
System function interfaces
1.6.1
Boot strapping pins
There are several boot configuration pins available on the module that must be set correctly during
boot, or the module may not boot properly. Table 1 shows the condition of the bootstrap signals that
determine the behavior of the module during the system startup.
☞
Boot strap pins are configured to the default state internally on the module and must NOT be
configured externally, unless otherwise stated.
Pin
State during boot
Default
Behavior
Description
27
0
ESP boot mode (factory boot)
ESP Factory boot
Mode/RMII clock line.
1
Pull-up
Normal Boot from internal Flash
32
0
Silent
Printout on UART0 TXD
during boot
1
Pull-up
UART0 TXD Toggling
36
0
VDD_SDIO=3.3V (Not allowed)
Internal flash voltage
1
10 k
Ω
pull-up
VDD_SDIO=1.8V
(VDD_SDIO should always be at 1.8 V)
Table 1: NINA-W1 series boot strapping pins
☞
Additional requirements apply to pin
27
, depending on the intended use-case for the module:
o
On NINA-W13/W15 modules, pin
27
must be in default state during the boot.
o
Care must be taken if an RMII interface is to be included in the application design. As pin
27
connect to the RMII, it is important that the pin is in the correct state during the module boot
and before the RMII interface turns on. See also
o
On NINA-W10 modules, pin
27
is used to enter the ESP bootloader. Consequently, this pin
must be exposed on a pin header (or similar) to flash the module.
☞
During boot, pin
32
controls if additional system information should be transmitted on the UART
interface during startup. After the system has booted, it is reconfigured to
SPI_CS,
the SPI chip
select signal.
☞
During boot, pin
36
controls the voltage level of the internal flash during startup. After the system
has booted, it is reconfigured to
SPI_MISO
, the SPI slave data output signal. It must NOT be pulled
down by an external MCU or circuitry.
For the timing and algorithm for the detection of the SPI and RMII interfaces, see also the “Data and
command interfaces” section in the NINA-W13 and NINA-W15 data sheets [2] [4].
1.7
Data interfaces
1.7.1
Universal asynchronous serial interface (UART)
For data communication and firmware upgrade purposes, NINA-W1 series modules support an
interface comprised of three UARTs. Each UART supports the following signals:
•
Data lines (
RXD
as input,
TXD
as output)
•
Hardware flow control lines (
CTS
as input,
RTS
as output)
•
DSR
and
DTS
set and indicate the system modes
