NINA-B1 series - System Integration Manual
UBX-15026175 - R06
Design-in
Page 34 of 48
3.4.2
Serial peripheral interface (SPI)
The layout of the SPI bus should be done so that noise injection and cross talk are avoided.
3.4.3
I
2
C interface
The layout of the I
2
C bus should be done so that noise injection and cross talk are avoided.
3.5
NFC interface
Ensure that the NFC pins are configured correctly. Connecting an NFC antenna to the pins
configured as GPIO will damage the module.
The NFC antenna coil must be connected differentially between NFC1 and NFC2 pins of the device.
Two external capacitors should be used to tune the resonance of the antenna circuit to 13.56 MHz.
The required tuning capacitor value is given by the below equations: An antenna inductance of Lant = 2
μ
H will
give tuning capacitors in the range of 130 pF on each pin. For good performance, match the total capacitance
on NFC1 and NFC2.
Figure 13: NFC antenna design
𝐶𝐶
𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
′
=
1
(2
𝜋𝜋
× 13.56
𝑀𝑀𝑀𝑀𝑀𝑀
)
2
𝐿𝐿
𝑎𝑎𝑡𝑡𝑡𝑡
𝑤𝑤𝑤𝑤𝑤𝑤𝑤𝑤
𝐶𝐶
𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
′
=
1
2
×
�𝐶𝐶
𝑝𝑝
+
𝐶𝐶
𝑖𝑖𝑡𝑡𝑡𝑡
+
𝐶𝐶
𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
�
𝐶𝐶
𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
=
2
(2
𝜋𝜋
× 13.56
𝑀𝑀𝑀𝑀𝑀𝑀
)
2
𝐿𝐿
𝑎𝑎𝑡𝑡𝑡𝑡
− 𝐶𝐶
𝑝𝑝
− 𝐶𝐶
𝑖𝑖𝑡𝑡𝑡𝑡
3.5.1
Battery protection
If the antenna is exposed to a strong NFC field, current may flow in the opposite direction on the supply due to
parasitic diodes and ESD structures.
If the battery used does not tolerate return current, a series diode must be placed between the battery and the
device in order to protect the battery.
3.6
General High Speed layout guidelines
These general design guidelines are considered as best practices and are valid for any bus present in the
NINA-B1 series modules; the designer should prioritize the layout of higher speed busses. Low frequency signals
are generally not critical for layout.
