NEO-5
-
Hardware
Integration
Manual
Preliminary
Design-In
GPS.G5-MS5-08003-A2
u-blox
proprietary
Page 13
your position is our focus
2.3.3 Display Data Channel (DDC)
A
DDC
interface
(
SDA2
/
SCL2
)
is
available
for
communication
with
the
host.
Pins
SDA2
and
SCL2
have
internal
pull-ups.
No
pull-up
resistors
are
required
if
the
module
is
used
as
a
DDC/I
2
C
slave
(see
Micro
Controller
V
CC
Module
SDA2
SCL2
SDA
SCL
VDDIO
Figure 4: Connecting Module as DDC Slave
No
Master
Mode:
External
memory
is
not
supported
at
this
time.
2.3.4 Synchronous Peripheral Interface (SPI)
The
SPI
interface
allows
to
interface
to
a
host
CPU.
In
slave
mode
a
single
chip
select
signal
enables
communication
with
the
host.
No
Master
Mode:
External
memory
is
not
supported
at
this
time.
2.4 I/O Pins
2.4.1 EXTINT0
EXTINT0
is
an
external
interrupt
pin
with
fixed
input
voltage
thresholds
independent
of
VCC
(see
the
NEO-5
Data Sheet
Leave
open
if
unused.
2.4.2 Configuration
Pins
(CFG_COM0, CFG_GPS0)
NEO-5Q
and
NEO-5M
provide
one
or
two
pins
for
boot-time
configuration.
These
pins
become
effective
immediately
after
start-up.
Once
the
module
has
started,
the
configuration
settings
may
be
modified
with
UBX
configuration
messages.
The
modified
settings
remain
effective
until
power-down
or
reset.
If
these
settings
have
been
stored
in
battery-backup
RAM,
then
the
modified
configuration
will
be
retained,
as
long
as
the
backup
battery
supply
is
not
interrupted.
Some
configuration
pins
are
shared
with
other
functions,
e.g.
SPI.
During
start-up,
the
module
reads
the
state
of
the
configuration
pins.
Afterwards
the
other
functions
can
be
used.
For
more
information
about
settings
and
messages
see
the
NEO-5 Data Sheet
