LEON-G100 / LEON-G200 - System Integration Manual
GSM.G1-HW-09002-G3
Preliminary
Design-In
Page 83 of 125
2
Design-In
2.1
Design-in checklist
This section provides a design-in checklist.
2.1.1
Schematic checklist
The following are the most important points for a simple schematic check:
DC supply must provide a nominal voltage at
VCC
pin above the minimum normal operating range limit.
DC supply must be capable to provide 2.5 A current bursts with maximum 400 mV voltage drop at
VCC
pin.
VCC
supply should be clean, with very low ripple/noise: suggested passive filtering parts can be inserted.
Connect only one DC supply to
VCC
: different DC supply systems are mutually exclusive.
V_CHARGE
and
CHARGE_SENSE
must be externally shorted (LEON-G200 only).
The DC supply used as charger must be voltage and current limited as specified (LEON-G200 only).
Do no leave
PWR_ON
floating: add a pull-up resistor to a proper supply (i.e.
V_BCKP
).
Check that voltage level of any connected pin does not exceed the relative operating range.
Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications.
Insert the suggested low capacitance ESD protection and passive filtering parts on each SIM signal.
Check UART signals direction, since the signal names follow the
ITU-T V.24 Recommendation
Add a proper pull-up resistor to a proper supply on each DDC (I
2
C) interface line, if the interface is used.
Capacitance and series resistance must be limited on each line of the DDC (I
2
C) interface.
Insert the suggested passive filtering parts on each used analog audio line.
Check the digital audio interface specifications to connect a proper device.
For debug purposes, add a test point on each I
2
S pin and on
GPIO1
also if they are not used.
Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k
Ω
resistor on
the board in series to the GPIO when those are used to drive LEDs.
To avoid an increase of module current consumption in power down mode, any external signals
connected to the module digital pins (UART interface,
HS_DET
, GPIOs) must be set low or tri-stated
when the module is in power down mode.
Any external signal connected to the UART interface, I
2
S interfaces and GPIOs must be tri-stated when
the module is in power-down mode, when the external reset is forced low and during the module
power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and let a
proper boot of the module.
Provide proper precautions for ESD immunity as required on the application board.
All the not used pins can be left floating on the application board.
2.1.2
Layout checklist
The following are the most important points for a simple layout check:
Check 50
Ω
impedance of
ANT
line.
Follow the recommendations of the antenna producer for correct antenna installation and deployment
(PCB layout and matching circuitry).
Ensure no coupling occurs with other noisy or sensitive signals (primarily MIC signals, audio output
signals, SIM signals).
VCC
line should be wide and short.
