LEA-6 / NEO-6 - Hardware Integration Manual
GPS.G6-HW-09007-A
Preliminary
Appendix
Page 56 of 62
C
Interface Backgrounder
C.1
DDC Interface
Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus.
These lines are connected to all devices on the DDC. SCL is used to synchronize data transfers and SDA is the
data line. Both SCL and SDA lines are "open drain" drivers. This means that DDC devices can only drive them
low or leave them open. The
pull-up resistor (Rp) pulls the line up to V
DD
if no DDC device is pulling it down to
GND. If the pull-up resistors are missing, the SCL and SDA lines are undefined and the DDC bus will not work.
For most DDC systems the low and high input voltage level thresholds of SDA and SCL depend on V
DD
. See the
LEA-6 Data Sheet
[1] or
NEO-6 Data Sheet
[2] for the applicable voltage levels.
DDC Device A
DDC Device B
V
DD
SDA
SCL
GND
Rp
Rp
SDA in
SDA out
SCL in
SDA out
SDA in
SDA out
SCL in
SDA out
Figure 43: A simple DDC connection
The signal shape and the maximum rate in which data can be transferred over SDA and SCL is limited by the
values of Rp and the wire and I/O capacitance (Cp). Long wires and a large number of devices on the bus
increase Cp, therefore DDC connections should always be as short as possible. The resistance of the pull-up
resistors and the capacitance of the wires should be carefully chosen.
Figure 44: DDC block diagram
C.1.1
Addresses, roles and modes
Each device connected to a DDC is identified by a unique 7-bit address (e.g. whether it’s a microcontroller,
EEPROM or D/A Converter, etc.) and can operate as either a transmitter or receiver, depending on the function
Rp
Rp
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