JODY-W2 - System integration manual
UBX-18068879 - R14
System description
Page 13 of 84
C1 - Public
Rail
Allowable Ripple (peak to peak)
2
over DC supply
Current consumption, peak
10-100 kHz
100 kHz-1 MHz
>1 MHz
VBAT (3.3 V)
65 mV
pk-pk
25 mV
pk-pk
10 mV
pk-pk
0.8 A
VIO + 1V8
65 mV
pk-pk
25 mV
pk-pk
10 mV
pk-pk
300 mA + sink current to other devices
Table 5: Summary of voltage supply requirements
JODY-W2 series modules are powered by one of the following DC supplies:
•
Switching Mode Power Supply (SMPS)
•
Low Drop Out (LDO) regulator
The SMPS is the ideal choice when the available primary supply source has significantly higher value
than the operating supply voltage of the JODY-W2 series modules. The use of SMPS provides the
best power efficiency for the overall application and minimizes current drawn from the main supply
source.
⚠
When choosing the SMPS, ensure that the AC voltage ripple at switching frequency does not
exceed the requirements as specified in
. The use of an LDO linear regulator is convenient
for a primary supply with a relatively small difference to the supply voltage where the typical
85-90% efficiency of the switching regulator leads to minimal current saving. Linear regulators
are not recommended for high voltage step-down as they dissipate a considerable amount of
energy.
Independent of the selected DC power supply, it is crucial that it can handle the high peak current
generated by the module. A margin of at least 20% over the specified peak current is recommended
when designing the power supply for the module.
1.3
System function interfaces
Power-up sequence
The module power-up sequence can be initiated by applying the respective voltage to the
VBAT/VIO/1V8
supply pins and deasserting
PDn
(logic level 1) and
CORE_PDn
(logic level 1). Firmware
download is required every time
PDn
and
CORE_PDn
signals are asserted. It is advisable to tie
PDn
and
CORE_PDn
together.
JODY-W2 includes an internal SMPS voltage generator followed by an internal LDO which generates
the supply voltage to the supply nodes of the internal ASIC.
shows the recommended power-up sequence of the module. With
VIO
set to
3.3V, VIO
must
be applied before
VBAT
. With
VIO
set
to
1.8 V,
the order of
VIO
and
VBAT
does not matter. Once the
internal Switched Mode Power Supply (SMPS) has stabilized to 90% (taking up to 1.15 ms),
1V8
can
be applied followed by the de-assertion of
PDn
and
CORE_PDn.
PG
is an open-drain output used to sense when the internal DC/DC has stabilized. The output is set in
a high-impedance state when the internal voltage is "good". An external 1
00 kΩ pull
-up resistor must
be connected to
PG
to ensure that the signal is in an affirmative logic-high level. A low-level state
indicates that the power is “not good”. External power
-up logic can monitor the transition of
PG
to
high or wait at least 1.15 ms before applying 18V and continuing the power-up sequence.
2
Ripple measured on the power connectors of u-blox EVK.
