Tynemouth
MINI PET 40/80
12
V1.82
SCHEMATICS AND THEORY OF OPERATION
6502 CPU
The heart of the Mini PET is the 6502 processor. Here a WDC W65C02S is used. This is a modern version of the
NMOS 6502. It is not pin compatible and the read / write timing differs, so an original chip cannot be used with
the Mini PET (nor can anything that would plug into the CPU socket).
The main changes here from the PET schematic are the removal of a number of buffer chips. The minimised
chip count within the Mini PET reduces the loading on the address and data bus pins so they are no longer
necessary.
RAM AND ROM
The Mini PET has the full 32K of RAM a PET can support (without paging). This is provided by a single 32K chip,
which is decoded simply using the A15 line of the CPU to occupy 0000-7FFF. The ROM is mapped in 32K chunks
with 1000-7FFF in the ROM being mapped into the address space as 9000-FFFF. Up to 8 sets of 32K ROM
images can be stored in a 27C020 ROM chip and selected using the ROM switches. A17 is controlled by the
40/80 line, as the ROMs need to be different to support 40 or 80 column modes, this avoids ending up with the
wrong ROM for the currently selected screen mode.