TYAN S2925, Manual

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Feature Option Description
CPU Configuration
Module Version
AGESA Version
Physical Count
Logical Count
Read only Displays information about CPU
Revision
Cache L1
Cache L2
Speed
Current FSB Multiplier
Maximum FSB Multiplier
Able to change Freq.
uCode Patch Level
Read only Displays information about CPU
Disabled
GART Error Reporting
Enabled
This option should remain disabled
for normal operation. The driver
developer may enable it for the
purpose of testing.
Continuous
MTRR Mapping
Discrete
This option determines the method
used for programming CPU
MTRRs when 4GB or more of
memory is preset. Discrete leaves
the PCI hole below the 4GB
boundary undescribed.
Continuous explicitly describes the
PCI hole as non-cacheable.