S1856 Tomahawk BX/A+
55
BIOS
PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer. Burstable
transactions then burst on the PCI bus; nonburstable transactions do not.
PCI Master 0 WS Write
When this field is Enabled, writes to the PCI bus are executed with zero wait
states.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transaction cycles. Select Enabled to support compliance with PCI specifica-
tion version 2.1.
PCI Master Read Prefetch
A prefetch occurs during a read operations process when the controller
“peeks” at the next instruction and actually begins the next read instruction.
When this field is Enabled, the PCI bus master device is allowed to prefetch
the next read instruction and initiate the next read operation.
PCI#2 Access #1 Retry
Select Enabled to rotate priority of PCI masters.
AGP Master 1 WS Write
Select Enabled to add one clock tick to AGP write operations.
AGP Master 1 WS Read
Select Enabled to add one clock tick to AGP read operations.
PCI IRQ Activated By
Leave the IRQ trigger set at Level unless the PCI device assigned to the
interrupt specifies Edge-triggered interrupts.
Assign IRQ for USB
Assign an IRQ number to the onboard USB port.
Assign IRQ for VGA
Assign an IRQ number to your VGA adapter.
Assign IRQ for ACPI
Assign an IRQ number to ACPI.
