33
S1468-001-01
w
w
DRAM Read/Write Burst Timing
This sets the timing for Burst mode reads from DRAM. Burst read and
write request are generated by the CPU in four separate parts. The
"x" is the leadoff cycle and is determined by the chipset and the memory
timing. The remaining four numbers is the actual data cycles. The lower
the timing numbers, the faster the system will address memory.
The default for read burst timing is x2222.
The default for write burst timing is x3333.
w
w
System BIOS Cacheable
When enabled, accesses to the system BIOS ROM addressed at
F0000H-FFFFFH are cached. Enable this for best performance under
DOS/Windows or Windows95. When using operating systems that do
not access the BIOS (Unix, OS/2, NT, etc...) this setting can be
disabled.
The default is enabled.
w
w
Video BIOS Cacheable
As with caching the system BIOS above, enabling the Video BIOS
cache will cause access to the video BOS addressed at C0000h to
C7FFFFh to be cached.
The default is enabled.
w
w
8 bit I/O Recovery Time
The recovery time is the length of time measured in CPU clocks, which
the system will delay after the completion of an I/O request. This delay
takes place because the CPU is operationg so much faster than the
I/O bus that the CPU must be delayed to allow for the completion of the
I/O request. This option allows you to determine the recovery time
allowed for 8 bit I/O.
The default is 1 clock cycle.
w
w
16 bit I/O Recovery Time
This option allows you to determine the recovery time allowed for 16 bit
I/O.
The default is 1 clock cycle.
