TX Techniques TX FM1, Technical Manual

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TX-FM1/S/R/A Technical Manual www.txtechniques.co.uk
6.4 Stereo Encoder/RDS Encoder
IC6 contains outputs a 19kHz, 38kHz and 57kHz clock from a single crystal, XTAL 4.
RC filtering converts the digital pulses into sine waves.
IC7 creates the MPX signal with a suppressed carrier, the output of which is switched
by IC5. The 19kHz pilot signal is also switched by IC5 and then mixed to the
multiplex signal by IC8, a quad op-amp.
IC4 monitors the bridged (mono) audio from the ALC board for DTMF tones and
outputs serial data representing the decoded tones. IC3 is the main RDS processor;
a powerful 8-bit microcontroller capable of executing 5 million instructions every
second. It not only calculates and outputs the RDS data stream and the associated
Cyclic Redundancy Code in real time, but also contains an algorithm to decipher the
DTMF code validity, and sets the TA flag accordingly. The serial RDS data stream is
clocked out of IC3 by IC2 which digitally synthesises the RDS pulses. IC1 creates the
RDS signal with a suppressed carrier.
6.5 Modulator
The MPX signal modulates VCD1. The RF carrier frequency is tuned by a PLL voltage
across VCD3 and VCD4. The amount of capacitance effect the modulation varicap
has on the tuned circuit (VCD3, VCD4 and L1) is controlled by VCD2 in order to
introduce more modulation at one end of the tuning range. This has the effect of
maintaining a constant modulation level across the entire FM band. TR2 and TR3
form a ‘Cascode’ oscillator, which is buffered by TR4, and switched by TR5. This
allows the exciter output to be muted via the font panel LCD menu settings, during
tuning, and under output mismatch conditions.
An RF transformer T1 matches the buffer to the modulator output transistor TR6
which provides an efficient 2W (nominal) output.
IC2 provides the PLL tuning function, and is controlled by serial data from the host
microcontroller, IC3, which also continually monitors the PLL for a locked condition,
creating a logic output signal accordingly. An op-amp PLL filter is used based on
designs in the PLL IC manufacturer’s datasheet and application notes.
A voltage sample, proportional to the RF output power, is connected to PL3. This
controls the base of TR1. The more positive its base, the more OR1 reduces the
resistance on the VADJ pin of regulator VREG1. This lowers the voltage to TR4 and
TR6, lowering the modulator board’s output, thus forming an ALC function, the
threshold of which is controlled by VR1.
6.6 LCD Control Panel
IC1 is a microcontroller containing proprietary firmware to perform all metering,
system monitoring and set-up functions. D1, D2, R1 and C15 form a simple passive
rectifier with a time constant which creates a voltage proportional to the peak of the
bridged (mono) audio feed at PL3. This voltage is sampled by an on-chip D to A
converter in IC1.
5V logic control signals for TA function and MPX settings (on or off) are provided on
PL1.