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TUL PYNQ-ZU, Reference Manual

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26 

 

  

 

 

 

Figure 3-12 System Block Diagram 

 
 

Audio & Jack 

XCZU5EG Pin 

Net Name 

USB5744 

K14

 

AUDIO_DOUT

 

ADC_SDATA/GPIO1

 

H13

 

AUDIO_DIN

 

DAC_SDATA/GPIO0

 

E15

 

AUDIO_BCLK

 

BCLK/GPIO2

 

F15

 

AUDIO_WCLK

 

LRCLK/GPIO3

 

H14 

AUDIO_ADR0

 

ADR0/CLATCH

 

G14 

AUDIO_ADR1

 

ADR1/CDATA

 

PS_MIO18 

AUDIO_SDA

 

SDA/COUT

 

PS_MIO19 

AUDIO_SCL

 

SCK/CCLK

 

G15 

AUDIO_MCLK

 

MCLK

 

Summary of Contents for PYNQ-ZU

Page 1: ...1 PYNQ ZU Reference Manual v1 2...

Page 2: ...requirements document diagram Update the board picture 06 17 2021 V1 1 Updated Contents Update final image Add labels for main components Add Board Component Description Updated Block Diagram of Boar...

Page 3: ...es 9 Board Specifications 10 Dimensions 10 Board Component Descriptions 10 Power 10 Boot Mode Selection 12 PS Connected Peripherals 13 Clock Sources 13 DRAM 14 Micro SD 15 PS I2C MUX 16 PS Composite U...

Page 4: ...4 User I O 27 MIPI CSI 30 PMOD 31 FMC LPC 32 Dual SYZYGY Standard Ports 34 GROVE Interface 37 Raspberry Pi GPIOs 37 TPM PMOD 39 External Analog Inputs 39...

Page 5: ...source framework To find out more about PYNQ please see the project webpage at www pynq io Here you will find materials to help you get started with PYNQ and a forum for contacting the supporting comm...

Page 6: ...ZYGY Standard connector x2 8 40 Pin Raspberry PI connector 9 Power switch 10 Power IN 11 Pmod x1 PS Pmod TPM 12 Micro USB UART 13 MicroSD 14 USB 3 0 Hub 15 Composite USB 3 0 16 Mini Display Port 17 Au...

Page 7: ...ing Vivado IPI Vivado Vitis HLS and Vitis embedded development software Domain experts software engineers developers who like to develop applications in Python using PYNQ framework or C C language Tar...

Page 8: ...8 Block Diagram The PYNQ ZU board block diagram is shown in Figure 1 2 Figure 1 2...

Page 9: ...lock GTR DP Clock PS Connected peripherals Micro USB UART MicroSD 4GB DDR4 Composite USB 3 0 USB 3 0 Hub Mini Display Port Wifi BT User LEDs x2 XADC pins x2 Pmod x1 PS Pmod TPM Grove connectors x1 PL...

Page 10: ...10 Board Specifications Dimensions Width 180mm Length 130mm Board Component Descriptions Power The PYNQ ZU must be powered from an external 12V DC power supply The Power Jack is DC IN...

Page 11: ...11 Power switch is shown in Figure 3 1 Figure 3 1 DC IN Power switch...

Page 12: ...boot modes The boot mode is selected using the JTAG SD DIP switch To select the JTAG mode slide the switch to the left To select MicroSD mode slide the switch to the right The switch is shown in Figu...

Page 13: ...e sourced Table 3 1 Clock Name Frequency Clock Source Fixed Frequency Clock GTR_REF_DP_CLK 27MHz Si5340A Clock Generator GTR_REF_USB30_CLK 26MHz FPGA_CLK125 125MHz FPGA_USER_CLOCK 156 25MHz PS_REF_CLK...

Page 14: ...of 1GB The four modules combine to provide a 64 bit data path The DDR4 is connected to the hard memory controller in the Processor Subsystem PS The PS DDR4 memory controller supports speeds of up to 2...

Page 15: ...D0 An SD card can be used to boot the board or for applications that require non volatile external memory storage MIO Name 13 MIO13_SDIO_D0 14 MIO14_SDIO_D1 15 MIO15_SDIO_D2 16 MIO16_SDIO_D3 21 MIO21_...

Page 16: ...Bus Topology I2C Mux Addr 0x75 Port I2C BUS Device I2C Address 0 PMBUS attached device dependent 1 Si5340A Clock 0x74 2 AUDIO 0x6E 3 CAM MIPI attached device dependent 4 SYZYGY Port A 0x32 Port B 0x3...

Page 17: ...B3320 PHY is implemented through the IP in the XCZU5EG MPSoC Processor System PS USB 2 0 ULPI Upstream Connections to the XCZU5EG MPSoC XCZU5EG Pin Net Name USB3320 Pin Number Pin Name AB21 P16 USB_RS...

Page 18: ...Figure 3 6 Microchip USB5744 4 Port SuperSpeed High speed USB Controller Smart Hub provides low power OEM configurability and advanced features for embedded USB applications All enabled downstream po...

Page 19: ...C19 MIO70_USB1_STP 29 STP A18 MIO65_USB1_DIR 31 DIR E19 MIO64_USB1_CLK 1 CLKOUT B18 MIO67_USB1_NXT 2 NXT C18 MIO68_USB1_DATA0 3 DATA0 D19 MIO69_USB1_DATA1 4 DATA1 G19 MIO66_USB1_DATA2 5 DATA2 B19 MIO7...

Page 20: ...which is translated from single ended MIO signals to the differential DisplayPort AUX channel Wifi BT The PYNQ ZU contain a Wifi BT Module ATWILC3000 MR110CA The ATWILC3000 MR110CA module is an IEEE...

Page 21: ...MIO49_SD_DAT3 SD_DAT3 50 MIO50_SD_CMD SD_CMD 51 MIO51_SD_CLK SD_SCK 9 MIO9_UART1_RXD BT_TXD 8 MIO8_UART1_TXD BT_RXD 10 MIO10_BT_RTS BT_RTS 11 MIO11_BT_CTS BT_CTS 45 MIO45_WIFI_IRQN IRQN 4 MIO4_WIFI_CH...

Page 22: ...vice supports the dual mode standard version 1 1 type 1 and type 2 through the DDC link or AUX channel The HDMI video transmit block diagram is shown in Figure 3 10 Figure 3 9 HDMI Video RX The PYNQ Z...

Page 23: ...23 Figure 3 10 HDMI TX RX Diagram...

Page 24: ...X_LS_OE LS_OE D14 HDMI_TX_CT_HPD CT_HPD E13 HDMI_SI5324_RST RST_B Si5324C B15 HDMI_CTL_SDA SDA SDIO A15 HDMI_CTL_SCL SCL F13 HDMI_SI5324_LOL LOL G13 HDMI_SI5324_INT_ALM INT_C1B H4 HDMI_REC_CLOCK_P CKI...

Page 25: ...and Line IN Connector The ADAU1761 is a low power stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record The stereo audio ADCs and DACs support sample rates fro...

Page 26: ...Net Name USB5744 K14 AUDIO_DOUT ADC_SDATA GPIO1 H13 AUDIO_DIN DAC_SDATA GPIO0 E15 AUDIO_BCLK BCLK GPIO2 F15 AUDIO_WCLK LRCLK GPIO3 H14 AUDIO_ADR0 ADR0 CLATCH G14 AUDIO_ADR1 ADR1 CDATA PS_MIO18 AUDIO_S...

Page 27: ...Q ZU board provides these general purpose I O capabilities as shown in Figure 3 13 l Four user LEDs l Four user DIP switches l Four user push buttons l Two user RGBLEDs Figure 3 13 RGBLED LED x4 Pushb...

Page 28: ...e User I O A9 LED_B0 LEDRGB0 A5 LED_G0 A4 LED_R0 A8 LED_B1 LEDRGB1 B9 LED_G1 B6 LED_R1 B5 LED0 LED A6 LED1 B8 LED2 A7 LED3 AA12 SW0 DIP switches Y12 SW1 W11 SW2 W12 SW3 AH14 BTN0 Push buttons AG14 BTN...

Page 29: ...wn in Figure 3 14 MIPI CSI Pmods FMC LPC SYZYGY Standard Ports Grove Interface ports Raspberry PI GPIO TPM PMOD External Analog Inputs Figure 3 14 Extended IO SYZYGY Standard Ports Pmod Grove FMC LPC...

Page 30: ...Pin Number J6 Net Name 1 GND 2 GND D5 3 MIPI_LANE_N0 4 MIPI_LANE_N0 E5 5 MIPI_LANE_P0 6 MIPI_LANE_P0 7 GND 8 GND F6 9 MIPI_LANE_N1 10 MIPI_LANE_N1 G6 11 MIPI_LANE_P1 12 MIPI_LANE_P1 13 GND 14 GND D6 1...

Page 31: ...signals pins 6 and 12 two Ground signals pins 5 and 11 and eight 3 3V compliant logic signals as shown in Figure 3 15 Figure 3 15 Pmod Port PmodA Diagram XCZU5EG PIN Net Name T8 PMOD0_0 R8 PMOD0_1 V8...

Page 32: ...FMC_LPC_DP0_M2C_P P2 D5 FMC_LPC_GBTCLK0_M2C_N C7 FMC_LPC_DP0_M2C_N P1 D8 FMC_LPC_LA01_CC_P P7 C10 FMC_LPC_LA06_P J7 D9 FMC_LPC_LA01_CC_N P6 C11 FMC_LPC_LA06_N H7 D11 FMC_LPC_LA05_P J1 C14 FMC_LPC_LA1...

Page 33: ...MC_LPC_LA07_N H6 G18 FMC_LPC_LA16_P M8 H16 FMC_LPC_LA11_P K2 G19 FMC_LPC_LA16_N L8 H17 FMC_LPC_LA11_N J2 G21 FMC_LPC_LA20_P AB4 H19 FMC_LPC_LA15_P N9 G22 FMC_LPC_LA20_N AB3 H20 FMC_LPC_LA15_N N8 G24 F...

Page 34: ...ts The PYNQ ZU use the SYZYGY Standard interface to communicate with installed SYZYGY pods 2 SYZYGY standard interfaces available on the board Standard Peripheral as shown in Figure 3 16 Figure 3 16 S...

Page 35: ...SYZYGY1_DN2 AG11 16 S11_D5N SYZYGY1_DN5 AF13 13 S8_D4P SYZYGY1_DP4 AD15 18 S13_D7P SYZYGY1_DP7 AG13 15 S10_D4N SYZYGY1_DN4 AD14 20 S15_D7N SYZYGY1_DN7 AH13 17 S12_D6P SYZYGY1_DP6 AC14 22 S17 SYZYGY1_S...

Page 36: ...D2N SYZYGY2_DN2 G10 16 S11_D5N SYZYGY2_DN5 AB13 13 S8_D4P SYZYGY2_DP4 Y14 18 S13_D7P SYZYGY2_DP7 AB15 15 S10_D4N SYZYGY2_DN4 Y13 20 S15_D7N SYZYGY2_DN7 AB14 17 S12_D6P SYZYGY2_DP6 W14 22 S17 SYZYGY2_S...

Page 37: ..._GROVE_IO1 GC0 P9 PL_GROVE_IO2 AE4 PL_GROVE_IO3 GC1 AB5 PL_GROVE_IO4 Raspberry Pi GPIOs The PYNQ ZU has a 40 pin Raspberry Pi connector with 28 pins connected to the XCZU5EG device G D1 E7 C4 C2 A1 C8...

Page 38: ...pin connector pin FPGA pin 1 2 D2 3 4 F1 5 6 E1 7 8 F7 9 10 D4 E8 11 12 G1 G4 13 14 E9 15 16 F8 17 18 G8 B4 19 20 C9 21 22 A3 D9 23 24 B3 25 26 A2 C8 27 28 C7 A1 29 30 C2 31 32 B1 C4 33 34 E7 35 36 C1...

Page 39: ...5EG PIN Port number PS_MIO41 1 PS_MIO43 2 PS_MIO42 3 PS_MIO38 4 PS_MIO44 7 PS_MIO37 8 PS_MIO40 9 PS_MIO39 10 External Analog Inputs The PYNQ ZU provides an Analog Front End XADC block The XADC block i...

Page 40: ...40 Figure 3 17 XADC Block Diagram XADC XCZU5EG PIN Net Name AB7 AR_AN_P0 AB8 AR_AN_P1 AC7 AR_AN_N0 AC8 AR_AN_N1...

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