Transcend CompactFlash 300X Datasheet Download Page 17 | Manualshive

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300X CompactFlash Card

Transcend Information Inc.

V1.1

17

4) The -WAIT and IORDY signals shall be ignored by the host.

Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with
systems that do not support CF Advanced timing modes

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Summary of Contents for CompactFlash 300X

Page 1: ...C to 85 o C Storage Temperature 40 o C to 85 o C Operation Modes PC Card Memory Mode PC Card IO Mode True IDE Mode True IDE Mode supports Ultra DMA Mode 0 to Ultra DMA Mode 5 Ultra DMA mode 5 must use...

Page 2: ...T T TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 2 Transcend...

Page 3: ...T T TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 3 Block Diagram...

Page 4: ...12 A07 2 I I1Z 13 VCC Power 13 VCC Power 13 VCC Power 14 A06 I I1Z 14 A06 I I1Z 14 A06 2 I I1Z 15 A05 I I1Z 15 A05 I I1Z 15 A052 I I1Z 16 A04 I I1Z 16 A04 I I1Z 16 A04 2 I I1Z 17 A03 I I1Z 17 A03 I I...

Page 5: ...49 D101 I O I1Z OZ3 49 D101 I O I1Z OZ3 50 GND Ground 50 GND Ground 50 GND Ground Note 1 These signals are required only for 16 bit accesses and not required when installed in 8 bit systems Devices sh...

Page 6: ...ode I O 46 This signal is asserted high as BVD1 is not supported This signal is asserted low to alert the host to changes in the READY and Write Protect states while the I O interface is configured It...

Page 7: ...ts CSEL PC Card Memory Mode CSEL PC Card I O Mode CSEL True IDE Mode I 39 This signal is not used for this mode but should be connected by the host to PC Card A25 or grounded by the host This signal i...

Page 8: ...ed by the device In True IDE Mode DMARQ shall not be driven when the device is not selected in the Drive Head register While a DMA operation is in progress CS0 CE1 and CS1 CE2 shall be held negated an...

Page 9: ...y the host interface It is used to read data from the CompactFlash Storage Card in Memory Mode and to read the CIS and configuration registers In PC Card I O Mode this signal is used to read the CIS a...

Page 10: ...the host in response to DMARQ to initiate DMA transfers In True IDE Mode while DMA operations are not active the card shall ignore the DMACK signal including a floating condition If DMA operation is n...

Page 11: ...eceive Ultra DMA data out bursts The device may negate DDMARDY to pause an Ultra DMA transfer In all modes when Ultra DMA mode DMA Read is active this signal is the data in strobe generated by the dev...

Page 12: ...gger High level input voltage VIH 2 92 V Schmitt trigger 1 0 8 V Non schmitt trigger Low level input voltage VIL 1 70 V Schmitt trigger 1 Pull up resistance2 RPU 50 73 KOhm Pull down resistance RPD 50...

Page 13: ...ow values shall be met at the source connector to include the effect of series termination Table Input Characteristics UDMA Mode 4 Parameter Symbol MIN MAX Units DC supply voltage to drivers VDD3 3 3...

Page 14: ...o supply and sink current toVDD3 VoH2 VDD3 0 51 VDD3 0 3 Volts Voltage output low at 6 mA VoL2 0 51 Volts Notes 1 IoLDASP shall be 12 mA minimum to meet legacy timing and signal integrity 2 IoH value...

Page 15: ...Status Signal READY WAIT WP Pull up to VCC R 10 K 3 INPACK In PCMCIA PC Card modes Pull up to VCC R 10 K 4 In True IDE mode if DMA operation is supported by the host Pull down to Gnd R 5 6 K 5 PC Car...

Page 16: ...host shall be able to drive at least the following load 10 while meeting all AC timing requirements the number of sockets wired in parallel multiplied by 100pF with DC current 450 A low state and 150...

Page 17: ...pactFlash Card Transcend Information Inc V1 1 17 4 The WAIT and IORDY signals shall be ignored by the host Devices supporting CF Advanced timing modes shall also support slower timing modes to ensure...

Page 18: ...tra DMA modes Table describes typical values for series termination at the host and the device Table Typical Series Termination for Ultra DMA Signal Host Termination Device Termination IORD HDMARDY HS...

Page 19: ...l be no more than 0 5 shorter than either STROBE trace as measured from the IC pin to the connector Ultra DMA Mode Cabling Requirement Operation in Ultra DMA mode requires a crosstalk suppressing cabl...

Page 20: ...A tAVQV 300 Card Enable Access Time ta CE tELQV 300 Output Enable Access Time ta OE tGLQV 150 Output Disable Time from CE tdis CE tEHQZ 100 Output Disable Time from OE tdis OE tGHQZ 100 Address Setup...

Page 21: ...fications are shown in Table below Table Configuration Register Attribute Memory Write Timing Speed Version 250 ns Item Symbol IEEE Symbol Min ns Max ns Write Cycle Time tc W tAVAV 250 Write Pulse Wid...

Page 22: ...following OE th CE tGHEH 20 15 15 10 Wait Delay Falling from OE tv WT OE tGLWTV 35 35 35 na 1 Data Setup for Wait Release tv WT tQVWTH 0 0 0 na 1 Wait Width Time2 tw WT tWTLWTH 350 350 350 na 1 Notes...

Page 23: ...Hold Time th A tGHAX 20 15 15 15 CE Hold following WE th CE tGHEH 20 15 15 10 Wait Delay Falling from WE tv WT WE tWLWTV 35 35 35 na1 WE High from Wait Release tv WT tWTHWH 0 0 0 na1 Wait Width Time2...

Page 24: ...lowing IORD thA IORD tlGHAX 20 10 10 10 CE Setup before IORD tsuCE IORD tELIGL 5 5 5 5 CE Hold following IORD thCE IORD tlGHEH 20 10 10 10 REG Setup before IORD tsuREG IORD tRGLIGL 5 5 5 5 REG Hold fo...

Page 25: ...5 Address Setup before IOWR tsuA IOWR tAVIWL 70 25 25 15 Address Hold following IOWR thA IOWR tlWHAX 20 20 10 10 CE Setup before IOWR tsuCE IOWR tELIWL 5 5 5 5 CE Hold following IOWR thCE IOWR tlWHEH...

Page 26: ...RD high is 0 nsec but minimum IORD width shall still be met 1 t0 is the minimum total cycle time t2 is the minimum command active time and t2i is the minimum command recovery time or command inactive...

Page 27: ...T T TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 27...

Page 28: ...m inverted from their electrical states on the bus Item Mode 0 ns Mode 1 ns Mode 2 ns Mode 3 ns Mode 4 ns Note tO Cycle time min 480 150 120 100 80 1 tD IORD IOWR asserted width min 215 80 70 65 55 1...

Page 29: ...only during an Ultra DMA data burst during a DMA Write command 4 The HSTROBE and DSTROBE signals are active on both the rising and the falling edge 5 Address lines 03 through 10 are not used in True I...

Page 30: ...o default has been issued An Ultra DMA capable device shall clear any previously selected Ultra DMA mode and revert to the default non Ultra DMA modes after executing a power on or hardware reset Both...

Page 31: ...Min Max Min Max Min Max Min Max Min Max Min Max t2CYCTYP 240 160 120 90 60 40 Sender tCYC 112 73 54 39 25 16 8 Note 3 t2CYC 230 153 115 86 57 38 Sender tDS 15 0 10 0 7 0 7 0 5 0 4 0 Recipient tDH 5 0...

Page 32: ...time device 2 tCVS CRC word valid setup time at host from CRC valid until DMACK negation 3 tCVH CRC word valid hold time at sender from DMACK negation until CRC may become invalid 3 tZFS Time from ST...

Page 33: ...of the cable only in a configuration with a single device located at the end of the cable This could result in the minimum values for tDS and tDH for mode 5 at the middle connector being 3 0 and 3 9...

Page 34: ...ting the connector If the test point is on a cable conductor rather than the PCB an adjacent ground conductor shall also be cut within one half inch of the connector The test load and test points shou...

Page 35: ...EG OE WE A10 A9 A8 A4 A3 A2 A1 A0 SELECTED SPACE 1 1 X X X X X XX X X X X Standby and UDMA transfer X 0 0 0 1 0 1 XX X X X 0 Configuration Registers Read 1 0 1 0 1 X X XX X X X X Common Memory Read 8...

Page 36: ...0 0 0 0 or 1 RD Static Device Initiating BurstTermination 1 1 1 0 1 1 0 or 1 RD Static Host Acknowledement of Device Initiated Burst Termination 1 1 0 0 1 0 0 or 1 YES Static Host Initiating BurstTer...

Page 37: ...ion see section 4 3 18 Ultra DMA Mode Read Write Timing Specification Yes L1 H H X X X H H Odd Byte Even Byte Read Byte Access CIS ROM 8 bits No L H L2 L L L L2 H High Z Even Byte Write Byte Access CI...

Page 38: ...T T TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 38 Configuration Option Register Base 00h in Attribute Memory...

Page 39: ...T T TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 39 Card Configuration and Status Register Base 02h in Attribute Memory...

Page 40: ...T T TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 40 Pin Replacement Register Base 04h in Attribute Memory...

Page 41: ...T T TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 41 Socket and Copy Register Base 06h in Attribute Memory...

Page 42: ...torage responds The CompactFlash Storage Card may request the host to extend the length of an input cycle until data is ready by asserting the WAIT signal at the start of the cycle Function Code DMA C...

Page 43: ...ion Active 1 1 0 1 0 X or YES Static Burst Transfer 1 1 0 1 0 1 0 or 1 RD Static Data In Burst Host Pause 1 1 0 1 0 0 0 or 1 RD Static Data In Burst Device Pause 1 1 0 1 0 1 0 or 1 WR Static Data Out...

Page 44: ...s Don t Care H H H H L L L H L L H H High Z High Z Even Byte Odd Byte Byte Write 8 bits Don t Care H H H H L L L H H H L L Don t Care Don t Care Even Byte Odd Byte Word Read 16 bits Don t Care H L L X...

Page 45: ...mpactFlash Storage Cards may support the following optional detection methods 1 The card is permitted to monitor the OE ATA SEL signal at any time s and switch to PCMCIA mode upon detecting a high lev...

Page 46: ...ed such that a cable exceeding 0 15 meters is required to connect the host to the card The load presented to the Host by cards supporting Ultra DMA is more controlled than that presented by other Comp...

Page 47: ...h 3F6h 3F7h primary or 170h 177h 376h 377h secondary with IRQ 14 or other available IRQ b Any system decoded 16 byte I O block using any available IRQ c Memory space The communication to or from the C...

Page 48: ...TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 48 I O Primary and Secondary Address Configurations Table Primary and Secondary I O Deco...

Page 49: ...Transcend Information Inc V1 1 49 Contiguous I O Mapped Addressing When the system decodes a contiguous block of I O registers to select the CompactFlash Storage Card the registers are accessed in th...

Page 50: ...1 50 Memory Mapped Addressing When the CompactFlash Storage Card registers are accessed via memory references the registers appear in the common memory space window 0 2K bytes as follows True IDE Mod...

Page 51: ...additional information about the source of an error when an error is indicated in bit 0 of the Status register This register is also accessed in PC Card Modes on data bits D15 D8 during a read operati...

Page 52: ...s 1F5h 175h Offset 5 This register contains the high order bits of the starting cylinder address or bits 23 16 of the Logical Block Address Drive Head LBA 27 24 Register Address 1F6h 176h Offset 6 The...

Page 53: ...valid when this bit is set to a 1 During the data transfer of DMA commands the Card shall not assert DMARQ unless either the BUSY bit the DRQ bit or both are set to one Bit 6 RDY RDY indicates whethe...

Page 54: ...e host software should set this bit to 0 Bit 4 this bit is ignored by the CompactFlash Storage Card The host software should set this bit to 0 Bit 3 this bit is ignored by the CompactFlash Storage Car...

Page 55: ...conditionally tri state D7 of I 0 address 3F7h 377h when a CompactFlash Storage Card is installed and conversely to tristate D6 D0 of I O address 3F7h 377h when a floppy controller is installed 4 Do n...

Page 56: ...h Y Y Support 10 Key Management Structure Read B9 Feature 0 127 Y Y Y Y Y NOT Support 1 11 Key Management Read Keying Material B9 Feature 80 Y Y Y Y Y NOT Support 1 12 Key Management Change Key Manage...

Page 57: ...32h or 33h Y Y Y Y Not Support 2 39 Write Multiple C5h Y Y Y Y Y Support 40 Write Multiple w o Erase CDh Y Y Y Y Y Support 41 Write Sector s 30h or 31h Y Y Y Y Y Support 42 Write Sector s w o Erase 3...

Page 58: ...ostic command is issued in a PCMCIA configuration mode this command runs only on the CompactFlash Storage Card that is addressed by the Drive Head register This is because PCMCIA card interface does n...

Page 59: ...pact Flash Storage Card does not support the Flush Cache command the Compact Flash Storage Card shall return command aborted Bit 7 6 5 4 3 2 1 0 Command 7 E7h C D H 6 X Drive X Cyl High 5 X Cyl Low 4...

Page 60: ...card and aaaa indicates an ASCII string specific to the particular drive Word Address Default Value Total Bytes Data Field Type Information 848Ah 2 General configuration signature for the CompactFlash...

Page 61: ...ransfer cycle time In PC Card modes this value shall be 0h 67 XXXXh 2 Minimum PIO transfer cycle time without flow control 68 XXXXh 2 Minimum PIO transfer cycle time with IORDY flow control 69 79 0000...

Page 62: ...et using the definitions below and the Card is required to support for the CFA command set and report that in bit 2 of Word 83 Bit 15 12 values other than 8h and 0h are prohibited Bits 11 8 Retired Th...

Page 63: ...age Card supports IORDY operation If bit 11 is set to 0 then this CompactFlash Storage Card may support IORDY operation Bit 10 IORDY may be disabled Bit 10 shall be set to 0 indicating that IORDY may...

Page 64: ...tiword DMA modes 1 and 0 Bit 2 if set to one indicates that the CompactFlash Storage Card supports Multiword DMA modes 2 1 and 0 Support for Multiword DMA modes 3 and above are specific to CompactFlas...

Page 65: ...torage Card does not support this field the CompactFlash Storage Card shall return a value of zero in this field Words 82 84 Features command sets supported Words 82 83 and 84 shall indicate features...

Page 66: ...ted Bit 10 of word 85 shall be set to zero the Host Protected Area feature set is not supported Bit 11 of word 85 is obsolete Bit 12 of word 85 shall be set to one the CompactFlash Storage Card suppor...

Page 67: ...7 0 of word 91 contain the current Advanced Power Management level setting Word 128 Security Status Bit 8 Security Level If set to 1 indicates that security mode is enabled and the security level is m...

Page 68: ...sing the True IDE interface Notice The use of True IDE PIO Modes 5 and above or of Multiword DMA Modes 3 and above impose significant restrictions on the implementation of the host Additional Requirem...

Page 69: ...ant restrictions on the implementation of the host Additional Requirements for CF Advanced Timing Modes Bits 2 0 Maximum Advanced PCMCIA I O Mode Support Indicates the maximum I O timing mode supporte...

Page 70: ...tes the PC Card Memory or I O UDMA timing mode selected by the card Value PC Card Memory or I O UDMA timing mode Selected 0 PC Card I O UDMA mode 0 selected 1 PC Card I O UDMA mode 1 selected 2 PC Car...

Page 71: ...nd 7 95h or E1h C D H 6 X Drive X Cyl High 5 X Cyl Low 4 X Sec Num 3 X Sec Cnt 2 X Feature 1 X Initialize Drive Parameters 91h This command enables the host to set the number of sectors per track and...

Page 72: ...X Feature 1 X Read Buffer E4h The Read Buffer command enables the host to read the current contents of the CompactFlash Storage Card s sector buffer This command has the same protocol as the Read Sect...

Page 73: ...S S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 73 Read Multiple C4h Read Sector s 20h or 21h Read Verify Sector s 40h or 41h Recalibrate...

Page 74: ...S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 74 Request Sense 03h The extended error code is returned to the host in the Error Register S...

Page 75: ...l data transfers shall occur on the low order D 7 0 data bus and the IOIS16 signal shall not be asserted for data register accesses The host shall not enable this feature for DMA transfers Features 02...

Page 76: ...specifying a value in the Sector Count register The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value One PIO mode shall be selected at all times For Cards which...

Page 77: ...T T TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 77 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector Information...

Page 78: ...T T TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 78 Wear Level F5h Write Buffer E8h Write DMA CAh...

Page 79: ...TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 79 Write Long Sector 32h or 33h Write Multiple Command C5h Write Multiple without Erase...

Page 80: ...T T TS S S2 2 2G G G 1 1 16 6 6G G GC C CF F F3 3 30 0 00 0 0 300X CompactFlash Card Transcend Information Inc V1 1 80 Write Sector s 30h or 31h Write Sector s without Erase 38h Write Verify 3Ch...

Page 81: ...Parameters V V V Key Management Structure Read V V V V V V Key Management Read Keying Material V V V V V V Key Management Change Key Management Value V V V V V V NOP V V V V Read Buffer V V V V V Rea...

Page 82: ...ite Sector s w o Erase V V V V V V V V Write Verify V V V V V V V V Invalid Command Code V V V V V Error and Status Register summarizes the valid status and error value for all the CF ATA Command set...

Page 83: ...ommended polling time in minutes 375 385 R Reserved 386 395 F Firmware Version Date Code 396 397 F Number of initial invalid block 396 MSB 397 LSB 398 399 V Number of run time bad block 398 MSB 399 LS...

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