User's Manual l TQMaRZG2x UM 0100 l © 2021, TQ-Systems GmbH
Page 31
3.6
Reset
The reset logic contains the following functions:
•
Voltage monitoring on the TQMaRZG2x
•
External reset input
•
PGOOD output for power-up of circuits on the carrier board, e.g., PHYs
•
Reset LED (Function: PORESET# low: LED lights up)
Connector
Board
Controller
TQMARZG_RST_IN#
JTAG_SRST#
JTAG_TRST#
1.8 V
TRST#
PRESET#
PRESETOUT#
TQMARZG_RST_OUT#
3.3 V
BOOT_CFG#
PGOOD
&
RZ/G2x
Figure 12: Block diagram Reset structure
TQMARZG_RST_IN#
The reset signal controls the complete TQMaRZG2x. As soon as the signal has high level, the TQMaRZG2x starts.
The TQMaRZG2x starts as soon as the 5V input voltage is applied. By a diode on the TQMaRZG2x the signal
TQ_RST_IN# on the carrier board can be combined with other voltages. A LOW holds the TQMaRZG2x in reset.
BOOT_CFG#
BOOT_CFG# controls the boot strapping pins, respectively its driver. The signal is LOW during the reset phase and goes,
after PRESETOUT# became HIGH, delayed also on HIGH. This signals the carrier board that the boot strap signals can be
switched to high impedance.
PGOOD
PGOOD signals that the voltages on the carrier board can be switched on. PGOOD only becomes active when the
power sequencing on the TQMaRZG2x has successfully completed.
JTAG_SRST#
Depending on the debugger it is necessary to separate PRESET# and TRST# for JTAG access. For this reason the JTAG
debugger signal JTAG_SRST# is not connected to the RZ/G2x but to the board controller (3.3V). This causes a PRESET#
to be triggered. For the boundary scan test, TRST# must be able to be controlled independently of PRESET#.
JTAG_TRST#
TRST# of the debugger is directly connected to TRST# of the RZ/G2x. TRST# has a pull-up to 1.8V.
TQMARZG_RST_OUT#
TQMARZG_RST_OUT# is the status signal for the carrier board that the RZ/G2x is still held in reset.
TQMARZG_RST_OUT# is connected with PRESETOUT# of the RZ/G2x via an AND. This allows the board controller
to hold the periphery in reset in case of an error on the TQMaRZG2x.
