User's Manual l TQMaRZG2x UM 0100 l © 2021, TQ-Systems GmbH
Page 5
3.
ELECTRONICS
3.1
Interfaces to other systems and devices
3.1.1
Pin multiplexing
When using the processor signals the multiple pin configurations by different processor-internal function units must be taken
note of. The pin assignment in Table 4 and Table 5 refers to the
in combination with the MBaRZG2x.
Attention: Destruction or malfunction
Depending on the configuration many RZ/G2x pins can provide several different functions.
Please take note of the information concerning the configuration of these pins in (1), before
integration or start-up of your carrier board / Starterkit.
RFU:
Reserved pins without function. To support future module revisions,
these pins must not be connected.
3.1.2
Impedances
By default, all signals have a single-ended impedance of nominal 50 Ω ±10 %. Depending on the interface, other impedances are
also used on the TQMaRZG2x. The following table shows the affected interfaces:
Table 2:
Impedances
Interface
Signal type
Impedance TQMaRZG2x
Recommendation for carrier board
CSI
Clock + data
100 Ω differential
100 Ω ±10 % differential
HDMI
Clock + data
100 Ω differential
100 Ω ±10 % differential
LVDS
Clock + data
100 Ω differential
100 Ω ±10 % differential
PCIe
Clock
100 Ω differential
100 Ω ±10 % differential
PCIe / SATA
Data
90 Ω differential
90 Ω ±10 % differential
USB 2.0
Data
90 Ω differential
90 Ω ±10 % differential
USB 3.0
Clock
100 Ω differential
100 Ω ±10 % differential
Data
90 Ω differential
90 Ω ±10 % differential
3.1.3
Track length
The following table shows the track lengths of critical TQMaRZG2x interfaces:
Table 3:
Track lengths
Interface
Signal
RZ/G2x ball to TQMaRZG2x connector [mm]
USB 3.0
RX
22.7
TX
23.2
CLK
19.8
PCIe0
RX
24.0
TX
24.9
CLK
28.6
PCIe1
RX
34.8
TX
36.4
CLK
42.4
LVDS
CH[3:0]
26.0
CLK
26.0
HDMI
DATA[2:0]
35.0
CLK
35.0
CSI0
DATA[3:0]
17.5
CLK
17.5
CSI1
DATA[3:0]
14.0
CLK
14.0
