User's Manual l TQMa335xL UM 0101 l © 2019, TQ-Systems GmbH
Page 14
3.2.4.2
Gigabit Ethernet MAC
The AM335x provides a 10/100/1000 Mbit MAC Core.
Two Ethernet interfaces are routed to the TQMa335xL pads using the 3-port switch. The switch supports two MII, RMII and RGMII.
The following table shows the signals used.
Table 13:
RGMII1
TQMa335xL pad
Signal
Pad
Dir.
AM335x ball
M15
RGMII1_RCLK
MII1_RX_CLK
I/O
L18
R14
RGMII1_RCTL
MII1_RX_DV
I/O
J17
M16
RGMII1_RD3
MII1_RXD3
I/O
L17
M17
RGMII1_RD2
MII1_RXD2
I/O
L16
N16
RGMII1_RD1
MII1_RXD1
I/O
L15
N17
RGMII1_RD0
MII1_RXD0
I/O
M16
K15
RGMII1_TCLK
MII1_TX_CLK
I/O
K18
L15
RGMII1_TCTL
MII1_TX_EN
I/O
J16
K16
RGMII1_TD3
MII1_TXD3
I/O
J18
K17
RGMII1_TD2
MII1_TXD2
I/O
K15
L16
RGMII1_TD1
MII1_TXD1
I/O
K16
L17
RGMII1_TD0
MII1_TXD0
I/O
K17
Table 14:
RGMII2
TQMa335xL pad
Signal
Pad
Dir.
AM335x ball
P13
RGMII2_RCLK
GPMC_A7
I/O
T15
R14
RGMII2_RCTL
GPMC_A1
I/O
V14
T14
RGMII2_RD3
GPMC_A8
I/O
V16
U14
RGMII2_RD2
GPMC_A9
I/O
U16
T15
RGMII2_RD1
GPMC_A10
I/O
T16
U15
RGMII2_RD0
GPMC_A11
I/O
V17
R12
RGMII2_TCLK
GPMC_A6
I/O
U15
R13
RGMII2_TCTL
GPMC_A0
I/O
R13
T12
RGMII2_TD3
GPMC_A2
I/O
U14
U12
RGMII2_TD2
GPMC_A3
I/O
T14
T13
RGMII2_TD1
GPMC_A4
I/O
R14
U13
RGMII2_TD0
GPMC_A5
I/O
V15
3.2.4.3
GPMC / External memory bus
The AM335x provides a General Purpose Memory Controller (GPMC), whose pins are routed to the TQMa335xL pads.
The GPMC signals are routed to the TQMa335xL pads as secondary function. GPMC-CLK is multiplexed with MMC1-CLK.
Note: Signal overlapping
There is an overlapping with an eMMC signal.
GPMC-CLK is multiplexed with MMC1-CLK.
1: Currently not supported.