User's Manual l MBa57xx UM 0100 l © 2020, TQ-Systems GmbH
Page 27
4.2.8
LVDS
An LVDS display can be connected to the MBa57xx (4× TX pairs). Since the AM57xx processor does not have a native LVDS
interface, the LVDS signals are generated by an SN75LVDS83B transceiver connected to the parallel LCD interface.
The LVDS interface is routed to two DF19 connectors.
The first connector (30-pin, X54) provides the LVDS data signals as well as 3.3 V and 5 V.
The second connector (20-pin, X55) provides control lines and USB signals as well as 12 V and 5 V.
A High level at LVDS_SHDN# switches the LVDS transceiver on, a Low level at LVDS_SHDN# switches the LVDS transceiver off.
The LVDS transceiver is configured for 8-bit FORMAT-1 mode and operates at 65 MHz
.
Illustration 16:
Block diagram LVDS
Table 31:
Type of LVDS connectors
Connector
Manufacturer / Number
Description
X54
Hirose / DF19G-30P-1H
Board-to-Cable FFC connector, 30-pin, 1 mm pitch
X55
Hirose / DF19G-20P-1H
Board-to-Cable FFC connector, 20-pin, 1 mm pitch
2:
See Texas Instruments Data Sheet SN75LVDS83B.
