User's Manual l MBa7x UM 0101 l © 2020, TQ-Systems GmbH
Page 37
4.2.7
LVDS
An LVDS display can be connected to the MBa7x (4× TX pairs). Since the i.MX7 processor does not have a native LVDS interface,
the LVDS signals are generated by the SN75LVDS83B transceiver connected to the parallel LCD interface.
The LVDS interface is routed to two DF19 connectors.
The first connector (30-pin, X15) provides the LVDS data signals as well as 3.3 V and 5 V.
The second connector (20-pin, X16) provides control lines and USB signals as well as 12 V and 5 V.
A High level at LVDS_SHDN# switches the LVDS transceiver on, a Low level at LVDS_SHDN# switches the LVDS transceiver off.
The LVDS transceiver is configured for 8-bit FORMAT-1 mode and operates at 65 MHz
DF19
30-pin
(X15)
DF19
20-pin
(X16)
HSIC HUB
LCD
LVDS
HSIC
USB3
LCD_CMD
LVDS
Transceiver
ESD
protection
TQMa7x
GPIO
Expander
I2C
GPIO
ESD
protection
USB3
3.3 V & 5 V
12 V & 5 V
Figure 26: Block diagram LVDS
The characteristics of the interface are determined by the LVDS transmitter in the i.MX7.
More information can be taken from the Reference Manual of the respective i.MX7.
Figure 27: Position of LVDS connectors – X15, X16
11:
See Texas Instruments Data Sheet SN75LVDS83B.
