TXZ Family
Flash Memory
2018-06-05
32 / 120
Rev. 2.0
3.1.1.2. Address Bit Configuration in the Bus Write Cycle (Code Flash)
Please refer to “Table 3.3
Address bit configuration in the bus write cycle (Code flash)” with “Table 3.2
memory access using the internal CPU (code flash)”.
Specify addresses in the first bus cycle and later cycle based on address setting of bus write cycle of normal
command.
Table 3.3 Address bit configuration in the bus write cycle (Code flash)
[Normal command]
Address
Adr
[31:24]
Adr
[23:21]
Adr
[20:19]
Adr
[18:12]
Adr
[11:4]
Adr
[3:0]
Normal
command
Address setting of bus write cycle of normal command
0x5E
“000”
fixed
Area
0:00
1:01
2:10
"0”
Recommended
Command
"0”
Recommended
[Read/reset, ID-Read]
Address
Adr
[31:24]
Adr
[23:21]
Adr
[20:16]
Adr
[15:14]
Adr
[13:0]
Read/
reset
Address setting of 1
st
bus write cycle of Read/reset
0x5E
“000”
fixed
"0”
Recommended
ID-Read
IA: ID
address
(
address setting of the 4
th
bus write cycle of ID-Read
)
0x5E
“000”
fixed
"00000”
fixed
ID
address
"0”
Recommended
[Automatic chip erasing]
Address
Adr
[31:24]
Adr
[23:21]
Adr
[20:12]
Adr
[11:4]
Adr
[3:0]
Chip erasing
Address setting of
1
st
to 6
th
bus write cycle
of chip erasing
0x5E
“000”
fixed
"0”
Recommended
Command
"0”
Recommended
[Automatic area erasing]
Address
Adr
[31:24]
Adr
[23:21]
Adr
[20:19]
Adr
[18:0]
Area erasing
AA: Area Address (address setting of the 6
th
bus write cycle of area erase command)
0x5E
“000”
fixed
Area
0:00
1:01
2:10
"0”
Recommended
