CPU
RAM (8Kbytes)
Bit search module
DMA controller
(8ch)
Bus converter (32bits-16bits)
Clock control unit
(Watchdog timer)
Interrupt control
unit
DREQ0 to
DREQ2
DACK0 to
DACK2
EOP0 to
EOP2
X0
X1
RSTX
HSTX
INT0 to
INT5
NMIX
AN0 to AN3
AVcc
AVss/AVRL
AVRH
ATGX
SI0 to SI2
SO0 to SO2
SC0 to SC2
STRBIN
DVDSOS
STREQ/
DRVVLD
10-bit
A/D converter
(4 ch.)
UART (3ch)
Reload timer (3ch)
Port D,E,F
A/V I/F port
Flash memory
(510KB)
RAM(2Kbytes)
Port0 to port B
DRAM
controller
Bus
controller
Bus converter
(Harvard _ Princeton
D16 to D31
A00 to A24
RDX
WR0X,WR1X
RDY
CLK
BRQ
BGRNTX
CS0X to CS5X
RAS0
RAS1
CS0L
CS0H
CS1L
CS1H
DW0X
DW1X
3
3
3
/
/
/
/
/
/
/
/
/
/
/
/
4
6
3
3
3
16
25
2
6
R
-b
u
s
(1
6
b
it
s
)
C
-b
u
s
(3
2
b
it
s
)
D
-b
u
s
(3
2
b
it
s
)
I-
b
u
s
(1
6
b
it
s
)
U5 ZR36707TQC
I/O Buffers and Data Latches
Y-Decoder
EEPROM
Cell Array
X-Decoder
Address Buffer & Latches
Control Logic
Memory Address
CE#
OE#
WE#
DQ - DQ
15
0
U12 SST39VF800A
Summary of Contents for SD-2960SA
Page 6: ...CIRCUIT DIAGRAMS Power Supply Circuit Diagram ...
Page 13: ...Front Display Power Switch Circuit Diagram ...
Page 15: ...Front Display PC Board Front Display PC Board Top Side Front Display PC Board Bottom Side ...
Page 16: ...Main PC Board Main PC Board Top Side ...
Page 17: ...Main PC Board Mian PC Board Bottom Side ...
Page 27: ...EXPLODEDVIEWS MAIN UNIT ...
Page 28: ...DVD MECHANISM ...
Page 30: ...1 1 SHIBAURA 1 CHOME MINATO KU TOKYO 105 8001 JAPAN ...