Toshiba MM20E45, Technical Training Manual

Page: 17 / 90

2-7
4. I
2
C BUS INTERFACE OPERATION TIMING
As an example of I
2
C Bus interface operation timings,
control for a memory IC will be shown below.
4-1 Write Mode (1 Byte)
Slave address
Start bit issue
ACK signal
output
Word address
input
Word address
update
Stop bit issue
After completion of write operation
word address becomes the write
a1 and held at that value.
SDA
SCL
1
0
A
2
1
0
A
1
5 2 4 3 6
R/W
ACK(OUT)
WA
7
WA
6
WA
5
WA
4
WA
3
WA
2
WA
1
WA
0
7 8 9
ACK(OUT)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
ACK(OUT)
IN IN IN
Slave address
R/W command input
1
0 0
ACK signal
output ACK signal
output Write data
input
Fig. 2-1
4-2 Read Mode
SDA
SCL
Start bit issue
ACK signal
output Word address
input
R/W
ACK(OUT)
0 A
2
1 A
1
0 1
1 5 2 4 3 6 7 8 9
IN IN
WA
7
WA
6
WA
5
WA
4
WA
3
WA
2
WA
1
WA
0
0 A
2
1 A
1
1 0 0
R/W
ACK(OUT)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
ACK(IN)
IN OUT IN
1 5 2 4 3 6 7 8 9
ACK signal
input Read data
output
ACK signal
output
Slave address
R/W command input
Start bit issue
ACK signal
input
Slave address
R/W command input
0 0
Stop bit issue
Fig. 2-1