Toshiba MK3006GAL Specification Download Page 46

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360050398

Toshiba Corporation Digital Media Network Company

Page

157

Host terminating an Ultra DMA data out burst

DMARQ

(device)

DMACK-

(host)

STOP

(host)

DDMARDY-

(device)

HSTROBE

(host)

DD(15:0)

(host)

DA0, DA1, DA2,

CS0-, CS1-

ACK

MLI

CVS

ACK

IORDYZ

ACK

CRC

CVH

Summary of Contents for MK3006GAL

Page 1: ...al Media Network Company Page 1 of 157 2005 Copyright TOSHIBA Corporation All Rights Reserved 1 1 1 1 1 1 1 1 TOSHIBA TOSHIBA Hard Disk Drive Specification 1 8 inch Hard Disk Drive MK6006GAH 4006GAH 3006GAL Rev 04 REF 360050398 ...

Page 2: ...ny Page 2 of 157 2005 Copyright TOSHIBA Corporation All Rights Reserved Revision History 1 8 inch Hard Disk Drive MK6006GAH 4006GAH 3006GAL Product Specification Revision Date 00 2004 07 01 Initial issue 01 2004 08 10 02 2004 10 08 03 2005 02 25 04 2005 09 05 ...

Page 3: ...t safety information that must be carefully reviewed Indicates a potentially hazardous situation which if not avoided may result in minor injury or property damage NOTE Gives you helpful information Toshiba Corporation shall not be liable for any damage due to the fault or negligence of users fire earthquake or other accident beyond the control of Toshiba Corporation Toshiba Corporation shall not ...

Page 4: ...ng a serious influence on the safe maintenance of public function etc special consideration 3 must be given with regard to operation maintenance and management of the system 2 A system including equipment linked with human safety or having a serious influence on the safe maintenance of public function etc corresponds to the following A main equipment control system used in atomic power plants a sa...

Page 5: ...ll Rights Reserved Do not disassemble remodel or repair Disassembly remodeling or repair may cause injury failure or data loss Do not drop Dropping may cause injury Do not touch sharp edges or pins of the drive Sharp protrusions etc may cause injury Hold the drive by both sides when carrying it SAFETY ...

Page 6: ...this in the instruction manual etc of the system in which this device is used and ensure that users are made thoroughly aware of it Inserting or pulling out the drive when the power is turned on may cause damage to the drive Exchange the drive etc after the power of HDD is turned off Extreme shock to the drive may cause damage to it data corruption etc Do not subject the drive to extreme shock suc...

Page 7: ...1 Temperature 22 8 1 2 Humidity 22 8 2 VIBRATION 22 8 3 SHOCK 22 8 4 ALTITUDE 24 8 5 ACOUSTICS SOUND POWER 24 8 6 SAFETY STANDARDS 25 EMC ADAPTABILITY 26 8 7 MAGNETIC FIELDS 26 9 RELIABILITY 27 9 1 ERROR RATE 27 9 1 1 Non Recoverable Error Rate 27 9 1 2 Seek Error Rate 27 9 2 PRODUCT LIFE 27 9 3 REPAIR 27 9 4 PREVENTIVE MAINTENANCE PM 27 9 5 LOAD UNLOAD 28 10 HOST INTERFACE 29 10 1 CABLING 29 10 1...

Page 8: ...0 10 8 1 Nop 00h 61 10 8 2 Recalibrate 1xh 61 10 8 3 Flush Cache E7h 61 10 8 4 Flush Cache EXT EAh 61 10 8 5 Read Sector 20h 21h 62 10 8 6 Read Sector EXT 24h 62 10 8 7 Write Sector 30h 31h 63 10 8 8 Write Sector EXT 34h 63 10 8 9 Read Verify 40h 65 10 8 10 Read Verify EXT 42h 65 10 8 11 Write Verify 3Ch 66 10 8 12 Format Track 50h 66 10 8 13 Seek 7xh 67 10 8 14 Toshiba Specific 67 10 8 15 Execute...

Page 9: ... user password 140 10 9 3 Security mode operation from power on 141 10 9 4 Password lost 142 10 9 5 Command Table 143 10 10 SELF MONITORING ANALYSIS AND REPORTING TECHNOLOGY 144 10 10 1 Attributes 144 10 10 2 Attributes values 144 10 10 3 SMART function default setting 144 10 11 ADAPTIVE POWER MODE CONTROL 145 10 11 1 Performance Idle 145 10 11 2 Active Idle 145 10 11 3 Low Power Idle 145 10 11 4 ...

Page 10: ...10 6 1 REGISTER MAP 50 TABLE 10 6 2 DECODE LOGIC 50 TABLE 10 7 1 DIAGNOSTIC MODE ERROR REGISTER 53 TABLE 10 7 2 COMMAND CODE 58 TABLE 10 8 1 IDENTIFY INFORMATION 79 TABLE 10 8 2 IDENTIFY INFORMATION CONTINUED 80 TABLE 10 8 3 IDENTIFY INFORMATION CONTINUED 81 TABLE 10 8 4 IDENTIFY INFORMATION CONTINUED 82 TABLE 10 8 5 IDENTIFY INFORMATION CONTINUED 83 TABLE 10 8 6 SET MAX FEATURES REGISTER VALUES 9...

Page 11: ...ve for its small and light body The MK3006GAL MK4006GAH MK6006GAH consists of an HDA Head Disk Assembly and a printed circuit board The HDA has a sealed module which contains a disk spindle assembly a head actuator assembly and an air filtration system This HDA adopts Winchester technology which enhances high reliability The actuator is a rotary voice coil motor which enables high speed access The...

Page 12: ...steps such as backing up data etc without exception in order to prevent loss etc in cases where data loss may result in loss or damage Do not touch the top cover since application of force to it may cause damage to the drive Do not stack the drive on another drive or on other parts etc or stack them on top of it during storage or transportation Shock or weight may cause parts distortion etc Labels...

Page 13: ... second MK3006GAL MK6006GAH 265 megabits maximum per second MK4006GAH Read ahead cache and write cache enhancing system throughput Intelligent Interface ATA 2 ATA 3 ATA 4 ATA 5 ATA 6 interface supported Ultra100 supported Quick address conversion in translation mode Translation mode which enables any drive configuration LBA Logical Block Address mode Multi word DMA Ultra DMA modes and Advanced PIO...

Page 14: ...gigabytes 30 0058 60 0116 40 000 Number of sectors 58 605 120 117 210 240 78 126 048 Servo design method Sector Servo Recording method 60 61 ME2PR4 MNP Recording density Track mm TPI 4704 119 5k 4331 110k typ Bit mm BPI 31 8k 808k max 29 0k 737k max Flux change mm FRPI 32 3k 821k max 29 5k 750k max Number of disks 1 2 Number of data heads 2 4 Number of user data cylinders 55 728 38 160 Bytes per s...

Page 15: ...cal 20 sec Maximum Command Overhead msec 1 1 Under the condition of normal voltage 25oC normal temperature and bottom side down 2 Average time to seek all possible adjacent track without head switching 3 Weighted average time to travel between all possible combination of track calculated as below Weighted average access time Sum of P n t n Sum of P n n 1 to N Where N Total number of tracks P n Tot...

Page 16: ...leep 0 07 W Typical note 1 Under normal condition 25oC 101 3 kPa 1 013 mb and 3 3V 0 note 2 This is the maximum current value between power on to ready and the maximum value is the RMS Root Mean Square of 10 ms Dose not include rush current more information Figure 1 note 3 The seek average current is specified based on three operations per 100 ms note 4 The read write current is specified based on...

Page 17: ...consumption at Low power idle Capacity MK3006GAL 0 010 D MK4006GAH 0 0075 E MK6006GAH 0 005 E Energy consumption efficiency is calculated in accordance with the law regarding efficiency of energy consumption Energy saving law 1979 law number 49 Calculation of Energy consumption is dividing consumed energy by the capacity The consumed energy and capacity shall be measured and specified by the Energ...

Page 18: ...ntation The drive can be installed in all axes 6 directions 7 3 Mounting Instructions Take anti static measures in order to avoid damage to the drive when handling it The drive uses parts susceptible to damage due to ESD electrostatic discharge Wear ESD proof wrist strap in accordance with the usage specified when handling a drive that is not in an anti static protection bag Extreme shock to the d...

Page 19: ... temperature of top cover and the base must always be kept under 65 C to maintain the required reliability If the drive runs continuousely or spins up frequently the temperature of the top cover may rise to 15 C maximum If the drive is used in ambient temperature of 50 C or more it should be kept where adequate ventilation is available to keep the temperature of top cover under 65 C 6 Be careful w...

Page 22: ...on Under shipment 5 90 R H Packed in Toshiba s original shipping package Max wet bulb 29oC Operating 40oC Non operating 8 2 Vibration Operating 4 mm p p displacement 5 15 Hz No unrecoverable error 19 6 m s2 2 0G 15 500 Hz Sine wave sweeping 1 oct minute No unrecoverable error Non operating 10 mm p p displacement 5 15 Hz No unrecoverable error 49 m s2 5 0G 15 500 Hz Sine wave sweeping 1 oct minute ...

Page 24: ... MK4006GAH 16dB 18dB For idle mode Spindle in rotating 22dB 24dB Randomly select a track to be sought in such a way thatevery track has equal probability of being selected Seek rate ns is defined by the following formura ns 0 4 tT tL tT is published time to seek from one randam track to another without including rotational latency tL is the time for the drive to ratate by half a revolution Measure...

Page 25: ...SHIBA CORPORATION TOSHIBA CORPORATION TOSHIBA CORPORATION TOSHIBA CORPORATION TOSHIBA CORPORATION TOSHIBA CORPORATION MK6006GAH MK6006GAH E H011 04 2071 B E H011 04 2071 B E H011 04 2071 B 2004 06 2004 05 TOSHIBA CORPORATION TOSHIBA CORPORATION MK3006GAL TOSHIBA CORPORATION TOSHIBA CORPORATION E H011 04 2071 B 2004 05 2004 05 TOSHIBA CORPORATION TOSHIBA CORPORATION MK3006GAL E H011 04 2071 B E H01...

Page 26: ...4006GAH EN5008M1 E1 EN55022 1998 Class B EN50081 1 EN61000 3 2 1995 EN61000 3 3 1995 EN55024 EN61000 4 2 1995 EN61000 4 3 1995 ENV50204 1995 EN61000 4 4 1995 EN61000 4 5 1995 EN61000 4 6 1996 EN61000 4 11 1994 8 7 Magnetic Fields The disk drive shall work without degradation of the soft error rate under the following Magnetic Flux Density Limits at the enclosure surface MK3006GAL MK6006GAH MK4006G...

Page 27: ...A seek error is a positioning error recoverable by a retry including recalibration 9 2 Product Life Approximately 5 years or 20 000 power on hours whichever comes earlier under the following conditions Power on hours note1 Less than 333 hours month Operating note2 Less than 20 of power on hour Number of seek 1 30 x 106 seeks month Enviroment Normal 25oC 101 3 kPa 1 013 mb Do not apply electrical s...

Page 28: ...xecuted by the following commands Standby Standby Immediate Sleep Hard reset Load Unload is also executed as one of the idle modes of the drive If power is removed from the drive while the heads are over the media an Emergency Unload will take place An Emergency Unload is performed by routing the back EMF of the spindle motor to the actuator voice coil An Emergency Unload is mechanically much more...

Page 29: ...tober 26 1995 Information technology AT Attachment with Packet Interface Extension ATA 4 T13 1153D Revision 17 October 30 1997 Information technology AT Attachment with Packet Interface 5 Interface 5 ATA 5 T13 1321D Revision 2 December 13 1999 Information technology AT Attachment with Packet Interface 6 ATA 6 T13 1410D Revision 3b February 26 2002 10 1 Cabling 10 1 1 Interface Connector Drive side...

Page 30: ...C input output Characteristics 10 2 2 1 Input item Unit value voltage high note 1 V 2 0 to 5 5 low V 0 3 to 0 8 leak current µA 10 note 2 As non connected logic voltage input voltage level is from 0 3V to 0 5V note 1 The max input range of signal is from 0 3V to 5 5V note 2 Except for signal lines pulled up as shown in Table 10 3 3 1 10 2 2 2 Output item unit value Note voltage high V 2 4 min IOH ...

Page 31: ... Corporation Digital Media Network Company Page 31 of 157 2005 Copyright TOSHIBA Corporation All Rights Reserved 10 3 Interface connector 10 3 1 ATA interface connector UNIT mm Figure 4 ATA interface connector ...

Page 32: ...o SIGNALS 1 RESET 2 GROUND 3 DD 7 4 DD 8 5 DD 6 6 DD 9 7 DD 5 8 DD 10 9 DD 4 10 DD 11 11 DD 3 12 DD 12 13 DD 2 14 DD 13 15 DD 1 16 DD 14 17 DD 0 18 DD 15 19 GROUND 20 OPEN 21 DMARQ 22 GROUND 23 DIOW 24 GROUND STOP 25 DIOR 26 GROUND DMARDY HSTROBE 27 IORDY 28 CSEL DMARDY DSTROBE 29 DMACK 30 GROUND 31 INTRQ 32 IOCS16 33 DA 1 34 PDIAG CBLID 35 DA 0 36 DA 2 37 CS0 38 CS1 39 DASP 40 GROUND 41 3 3V 42 3...

Page 33: ...t has large value of pull up resistor CS0 and CS1 are also pulled up for better noise immunity Table 10 3 2 Signal treatment SIGNAL Driven by TYPE By host By drive RESET Host TP 10kΩPU DD 0 15 bi direction TS DMARQ Drive TS 5 6 k Ω PD DIOR Host TS DMARDY HSTROBE DIOW Host TS STOP IORDY Drive TS 4 7 k Ω PU DDMARDY DSTROBE CSEL Host GND 10 k Ω PU DMACK Host TP INTRQ Drive TS 10 k Ω PD IOCS16 Drive O...

Page 34: ...o indicate that the DMA data transfer is ready The direction of the data transfer is controlled by write read strobe signal HOST IOW or HOST IOR This signal is used on a hand shake manner with DMACK DIOW STOP O 23 Write strobe The rising clocks data from the host data bus HD0 through HD15 to a register or data register of the drive Stop signal used by the host after the completion of Ultra DMA Bur...

Page 35: ...eive a 16 bit data word open drain DA 1 O 33 Address line from the host system to select the registers of the drive PDIAG CBLID I O 34 In Master Slave mode this signal reports the presence of slave drive to master drive and enables transmitting of diagnostic result between master drive and slave drive DA 0 O 35 Address line from the host system to select the registers of the drive DA 2 O 36 Addres...

Page 36: ...in 70 25 tWCY Write Cycle Time min 600 383 240 180 120 tCICSV IOCS16 valid from CS max 90 50 40 n a n a tAICSV IOCS16 valid from address max 90 50 40 n a n a tAICSI IOCS16 inactive from address max 60 45 30 n a n a tA IORDY Setup time max 35 35 35 35 35 tB IORDY Pulse Width max 1250 1250 1250 1250 1250 IOCS16 shall be specified in ATA 2 specifications For other modes this signal is invalid The Dri...

Page 37: ...ead Cycle Time min 600 383 240 180 120 tCICSV IOCS16 valid from CS max 90 50 40 n a n a tAICSV IOCS16 valid from address max 90 50 40 n a n a tAICSI IOCS16 inactive from address max 60 45 30 n a n a tRD Read Data Valid to IORDY min 0 0 0 0 0 tA IORDY Setup time max 35 35 35 35 35 tB IORDY Pulse Width max 1250 1250 1250 1250 1250 IOCS16 is specified in ATA 2 specifications For other modes this sign...

Page 38: ...IONS Transfer mode MODE 0 MODE 1 MODE 2 Symbol Meaning Min Max Min Max Min Max t0 Cycle time 480 150 120 tC DMACK to DMARQ delay tD DIOW 16 bit 215 80 70 tG DIOW data setup 100 30 20 tH DIOW data hold 20 15 10 tI DMACK to DIOW setup 0 0 0 tJ DIOW to DMACK hold 20 5 5 tK DIOW negated pulse width 215 50 25 tL DIOW to DMARQ delay 40 40 35 tG tL DMACK tH tK tJ tI DMARQ DIOW DD15 DD0 tO tD ...

Page 39: ...ODE 0 MODE 1 MODE 2 Symbol Meaning Min Max Min Max Min Max t0 Cycle time 480 150 120 tC DMACK to DMARQ delay tD DIOR 16 bit 215 80 70 tE DIOR data access 150 60 50 tF DIOR data hold 5 5 5 tZ DIOR to tristate 20 25 25 tI DMACK to DIOR setup 0 0 0 tJ DIOR to DMACK hold 20 5 5 tK DIOR negated pulse width 50 50 25 tL DIOR to DMARQ delay 120 40 35 tE tL DMACK tF tK tJ tI DMARQ DIOR DD15 DD0 tO tD tZ ...

Page 40: ...Copyright TOSHIBA Corporation All Rights Reserved 10 4 5 Ultra DMA Timing Initiating an Ultra DMA data in burst DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 tZAD DA0 DA1 DA2 CS0 CS1 tUI tZAD tACK tACK tENV tENV tZIORDY tFS tFS tDVS tAZ tDVH tACK tZFS tDZFS ...

Page 41: ... data in burst tDVH tDVHIC DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 at host tCYC tCYC tDVS tDVSIC tDH tDHIC tDS tDSIC t2CYC t2CYC tDVH tDVHIC tDVH tDVHIC tDVS tDVSIC tDH tDHIC tDH tDHIC tDS tDSIC Host pausing an Ultra DMA data in burst DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 device tRFS tRP ...

Page 42: ...42 of 157 2005 Copyright TOSHIBA Corporation All Rights Reserved Device terminating an Ultra DMA data in burst tAZ tIORDYZ CRC DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tACK tLI tMLI tCVS tLI tACK tACK tZAH tCVH tSS tLI ...

Page 43: ...57 2005 Copyright TOSHIBA Corporation All Rights Reserved Host terminating an Ultra DMA data in burst tCVH CRC tAZ DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tACK tMLI tLI tLI tIORDYZ tACK tACK tZAH tMLI tCVS tRFS tRP ...

Page 44: ... Page 44 of 157 2005 Copyright TOSHIBA Corporation All Rights Reserved Initiating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tLI tDZFS tDVH tACK tACK tUI tDVS ...

Page 45: ...data out burst tDH tDHIC tDVH tDVHIC HSTROBE at host DD 15 0 at host HSTROBE at device DD 15 0 at device tCYC tCYC tDVS tDVSIC tDS tDSIC t2CYC t2CYC tDVH tDVHIC tDVH tDVHIC tDVS tDVSIC tDH tDHIC tDH tDHIC tDS tDSIC Device pausing an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tRFS tRP ...

Page 46: ...e 46 of 157 2005 Copyright TOSHIBA Corporation All Rights Reserved Host terminating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tLI tMLI tCVS tLI tLI tACK tIORDYZ tACK CRC tCVH tSS ...

Page 47: ...57 2005 Copyright TOSHIBA Corporation All Rights Reserved Device terminating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tMLI tCVS tLI tLI tACK CRC tCVH tACK tIORDYZ tMLI tRP tRFS ...

Page 48: ...0 5 0 5 0 tCVS CRC valid setup time 70 0 48 0 31 0 20 0 6 7 10 0 tCVH CRC valid hold time 6 2 6 2 6 2 6 2 6 2 10 0 tZFS Strobe released to driving 0 0 0 0 0 35 tDZFS Data released to driving 70 0 48 0 31 0 20 0 6 7 25 tFS First STROBE time 0 230 0 200 0 170 0 130 0 120 0 90 tLI Limit interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlock time min 20 20 20 20 20 20 tUI Unlimited interlock...

Page 49: ...ration All Rights Reserved 10 4 6 Reset Timing tM tN BUSY RESET Symbol Meaning Minimum Maximum Unit Condition tM RESET pulse width Low 25 µs tN RESET inactive to BSY active 400 ns 10 5 Grounding HDA Head Disk Assembly and DC ground ground pins on interface are connected electrically each other ...

Page 50: ... register Command register 1 0 0 X X High impedance Not used 1 0 1 0 X High impedance Not used 1 0 1 1 0 Alt status register Device control register 1 0 1 1 1 Device address register 1 Not used 1 1 X X X High impedance Not used X means don t care The host generates selection of two independent chips on the interface The selected high order chip HOST CS1 is valid only when the host is accessing the...

Page 51: ...fer for Read and Write operations The sector table during Format command and the data associated with the Identify Device command shall also be transferred to this register 10 7 1 1 Read Write command The register provides a high speed 16 bit path into the sector buffer with PIO and DMA 10 7 1 2 Read Write Buffer command This command provides 16 bit path between host and data buffer in the drive 1...

Page 52: ...eserved for use by removable media devices and indicates that new media is available to the operating system Bit 4 IDNF ID Not Found The requested sector could not be found Bit 3 MCR Media Change Requested is reserved for use by removable media devices and indicates that a request for media removal has been detected by the device Bit 2 ABRT Aborted Command This bit Indicates that the requested com...

Page 53: ...tomatically optimized by the drive internally This register is used with Set Features command 10 7 3 1 Smart command This command is used with the Smart commands to select subcommands 10 7 4 Sector Count Register CS0 DA2 DA0 2 Read Write 10 7 4 1 Disk Access command The sector count register determines the number of sectors to be read or written for Read Write and Verify commands A 0 in the sector...

Page 54: ...command Lower 8 bits of the starting cylinder number starting from 0 for Read Write Seek and Verify commands are contained in these registers After completion of the command or sector transfer the current cylinder is shown in this register In LBA mode Bits 8 15 of the target address in logical block address are set in this register After completion of a command the register is updated to reflect t...

Page 55: ...y selected head number 1 L 1 DEV HS3 HS2 HS1 HS0 Bit 7 Reserved recommended to set 1 Bit 6 L Select LBA mode L 0 CHS mode L 1 LBA mode Bit 5 Reserved recommended to set 1 Bit 4 DEV Device Select Drive0 Drive1 mode This bit is used to select the drive DEV 0 indicates the first fixed disk drive Drive0 and DEV 1 indicates the second Drive1 Single mode should be 0 If this is 1 a drive is not selected ...

Page 56: ...ommand execution and will be reset until the next command whether the drive condition is Ready or Not Ready Error bit is set on this occasion and will be reset just after power on and set again after the drive begins revolving at normal speed and gets ready to receive a command Bit 5 DF Device Fault DF 1 indicates that the drive has detected a fault condition during the execution of a Read Write c...

Page 57: ...r the drive to perform fixed disk operations Commands are executed when the TASK FILE is loaded and the command register is written and only when The status is not busy BSY is inactive and DRDY drive ready is active Any code NOT defined in the following list causes an Aborted Command error Interrupt request INTRQ is reset when a command is written The following are acceptable commands to the comma...

Page 58: ...O O O O X Write Multiple C5H O O O O O X Set Multiple Mode C6H O X X O X X Read DMA C8 C9H O O O O O X Write DMA CA CBH O O O O O X Power Control Stand by Immediate E0 94H O X X O X X Idle Immediate E1 95H O X X O X X Stand by E2 96H O X X O X X Idle E3 97H O X X O X X Check Power Mode E5 98H O X X O X X Sleep E6 99H O X X O X X Read Buffer E4H X X X O X X Flush Cache E7H X X X O X X Write Buffer ...

Page 59: ...RQ pin will be in a high impedance state whether a pending interrupt is found or not Bit 0 not used 10 7 13 Device Address register4 CS1 DA2 DA0 7 read only The device address register is a read only register used for diagnostic purposes The followings are definitions of bits for this register RSVD WTG HS3 HS2 HS1 HS0 DS1 DS0 Bit 7 Reserved high impedance Bit 6 WTG Write Gate This bit is active wh...

Page 60: ...MEDIATE INITIALIZE DEVICE PARAMETERS READ BUFFER READ DMA EXT READ MULTIPLE EXT READ NATIVE MAX ADDRESS EXT READ SECTOR S EXT READ VERIFY SECTOR S EXT RECALIBRATE SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK SEEK SET FEATURES SET MAX ADDRESS EXT SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK SET MAX FLEEZE LOCK SE...

Page 61: ...t BSY bit and move the R W heads on the disk to cylinder 0 At the completion of a seek it revises the status resets BSY and generates an interrupt 10 8 3 Flush Cache E7h COMMAND CODE 1 1 1 0 0 1 1 1 RESISTER SETTING DR drive no This command reports the completion of a Write cache to the host At the completion of a Write cache the drive revises the status resets BSY and generates an interrupt 10 8 ...

Page 62: ... interrupt is issued at the end of a command 10 8 6 Read Sector EXT 24h COMMAND CODE 0 0 1 0 0 1 0 0 REGISTER REGISTER SETTING NORMAL COMPLETION DR drive no no change LBA Low Current Previous LBA 7 0 LBA 31 24 HOB 0 HOB 1 last address last address LBA Mid Current Previous LBA 15 8 LBA 39 32 HOB 0 HOB 1 last address last address LBA High Current Previous LBA 23 16 LBA 47 40 HOB 0 HOB 1 last address...

Page 63: ...ddress where error has occurred 10 8 8 Write Sector EXT 34h COMMAND CODE 0 0 1 1 0 1 0 0 REGISTER REGISTER SETTING NORMAL COMPLETION DR drive no no change LBA Low Current Previous LBA 7 0 LBA 31 24 HOB 0 HOB 1 last address last address LBA Mid Current Previous LBA 15 8 LBA 39 32 HOB 0 HOB 1 last address last address LBA High Current Previous LBA 23 16 LBA 47 40 HOB 0 HOB 1 last address last addres...

Page 65: ...n an error occurs 10 8 10 Read Verify EXT 42h COMMAND CODE 0 1 0 0 0 0 1 0 REGISTER REGISTER SETTING NORMAL COMPLETION DR drive no no change LBA Low Current Previous LBA 7 0 LBA 31 24 HOB 0 HOB 1 last address last address LBA Mid Current Previous LBA 15 8 LBA 39 32 HOB 0 HOB 1 last address last address LBA High Current Previous LBA 23 16 LBA 47 40 HOB 0 HOB 1 last address last address SC Current P...

Page 66: ...et sector the command transfers the sector data from the host to the media After transferring the last data in the buffer it sets BSY and issues an Interrupt 10 8 12 Format Track 7 50h COMMAND CODE 0 1 0 1 0 0 0 0 REGISTER REGISTER SETTING NORMAL COMPLETION DR drive no no change CY cylinder to format no change HD head to format no change SN 01H SC 00H FT no change The track specified by the task f...

Page 67: ... REGISTER REGISTER SETTING NORMAL COMPLETION DR drive no no change CY cylinder to seek no change HD head to seek no change SN no change SC no change FT no change LBA address to seek no change This command moves the R W heads to the cylinder specified in the task files The drive sets BSY and starts seek operation After the completion of a seek operation the drive asserts DSC8 negates BSY and return...

Page 68: ...OH CY OOH HD OOH SN O1H SC O1H FT This command enables the drive to execute following self test and reports the results to the error register described in Table 10 7 2 1 1 ROM checksum test 2 RAM test 3 Controller LSI register test An interrupt is generated at the completion of this command When two drives are daisy chained on the interface both drives execute the self test and the Drive0 reports ...

Page 69: ...gical sectors per track which can be read by Identify Device Command On issuing this command the content of CY register shall not be checked This command will be terminated with ABORT error when it is issued on a invalid HD or SC register setting SC register 0 or the combination of HD and SC register exceeds the drive parameter Any drive access command should accompany correct HD SN register with ...

Page 70: ...sfer is determined by the contents of the Sector Number register and the Sector Count register The Sector Number register shall be used to extend the Sector Count register to create a 16 bit sector count value The Sector Number register shall be the most significant eight bits and the Sector Count register shall be the least significant eight bits A value of zero in both the Sector Number register...

Page 71: ...ltiple Mode command which shall be executed prior to the Read Multiple command When the Read Multiple command is issued the Sector Count Register contains the number of required sectors not the number of blocks or the block count If the number of required sectors is not evenly divisible by the block count The redundant sectors are transferred during the final partial block transfer The partial blo...

Page 72: ...sued Command execution is identical to the Write Sectors operation except that no interrupt is generated during the transfer of number of sectors defined by the Set Multiple Mode command but generated for each block DRQ qualification of the transfer is required only for each data block not for each sector The block count of sectors to be transferred without programming of intervening interrupts by...

Page 73: ...change HD no change SN no change SC The number of sectors block no change FT no change This command enables the drive to perform Read and Write Multiple operations and sets the block count for these commands The Sector Count Register is loaded with the number of sectors per block The drive supports 1 2 4 8 or16 sectors per block Upon receipt of the command the drive sets BSY 1 and checks the conte...

Page 74: ...nsfer During DMA transfer phase either BSY or DRQ is set to 1 When a command is completed CY HD SN register LBA register shows the sector transferred the latest If the drive detects unrecoverable error the drive terminate the command and CY HD SN register LBA register shows the sector where error occurred 10 8 24 Read DMA EXT 25h COMMAND CODE 0 0 1 0 0 1 0 1 REGISTER REGISTER SETTING NORMAL COMPLE...

Page 75: ...uring DMA transfer phase either BSY or DRQ is set to 1 When a command is completed CY HD SN register LBA register shows the sector transferred the latest If the drive detects unrecoverable error the drive terminates the command and CY HD SN register LBA register shows the sector where error has occurred 10 8 26 Write DMA EXT 35h COMMAND CODE 0 0 1 1 0 1 0 1 REGISTER REGISTER SETTING NORMAL COMPLET...

Page 76: ... spindle starts rotating and the drive executes read write operation After power on the spindle starts rotating and enters the idle mode During idle or stand by READY bit is set and the drive is ready to receive a command To be specific there are four different sub commands defined by lower 4 bits of command as follows The drive is in the idle mode when it is in default condition after power on 10...

Page 77: ...ero then stand by timer shall be enabled The value in SC shall be used to determine the time programmed into the stand by timer If SC is zero then the stand by timer is disabled Value in SC register Setting 0 Time out disabled 1 240 SC x 5 sec 241 251 value 240 x 30 min 252 21 min 253 Period between 8 and 12 hrs 254 Reserved 255 21 min 15 sec When the specified time period has expired the drive en...

Page 78: ...no no change CY no change HD no change SN no change SC 00H FT no change This command transfers a sector of data from the host to the specified 512 bytes of 128kB buffer of the drive When this command is issued the drive will set up the buffer for write operation and set DRQ The host may then write up to 512 bytes of data to the buffer 10 8 30 Identify Device ECh COMMAND CODE 1 1 1 0 1 1 0 0 REGIST...

Page 79: ...H Maximum number of sectors that can be transferred per interrupt on READ WRITE MULTIPLE commands 8010 48 Reserved 0000 49 Capabilities 15 14 Reserved 13 1 Standby timer values as specified in ATA ATAPI 6 specification are supported 0 Standby timer values are vendor specific 12 Reserved 11 1 IORDY supported 10 1 IORDY can be disabled 9 1 LBA supported 8 1 DMA supported 7 0 Reserved 2F00 50 Capabil...

Page 80: ...sfer Cycle Time 0078 67 Minimum PIO Transfer Cycle Time Without Flow Control ns 0078 68 Minimum PIO Transfer Cycle Time With IOCHRDY Flow Control 0078 69 79 Reserved for future command overlap and queuing 0000 80 Major version number 0000h or FFFFh device does not report version 15 7 Reserved for ATA 7 14 6 1 supports ATA ATAPI 6 5 1 supports ATA ATAPI 5 4 1 supports ATA ATAPI 4 3 1 supports ATA 3...

Page 81: ...et supported 2 1 Media serial number supported 1 1 SMART self test supported 0 1 SMART error logging supported 6023 85 Command set feature enabled 15 Reserved 14 1 NOP command enabled 13 1 READ BUFFER command enabled 12 1 WRITE BUFFER command enabled 11 Reserved 10 1 Host Protected Area feature set enabled 9 1 DEVICE RESET command enabled 8 1 SERVICE interrupt enabled 7 1 release interrupt enabled...

Page 82: ... result Device 0 shall clear these bits to zero Device 1 shall set these bits as follows 12 Reserved 11 0 Device 1 did not assert PDIAG 1 Device 1 asserted PDIAG 10 9 These bits indicate how Device 1 determined the device number 00 Reserved 01 a jumper was used 10 the CSEL signal was used 11 some other method was used or the method is unknown 8 1 Fixed 7 0 Device 0 hardware reset result Device 1 s...

Page 83: ... Reserved 0000 128 Security status 15 9 Reserved 8 Security level 0 High 1 Maximum 7 6 Reserved 5 1 Enhanced security erase supported 4 1 Security count expired 3 1 Security frozen 2 1 Security locked 1 1 Security enabled 0 1 Security supported 0XXX 129 159 Reserved 0000 160 CFA power mode 1 15 Word 160 supported 14 Reserved 13 CFA power mode 1 is required for one or more commands implemented by t...

Page 84: ...quires SET FEATURES subcommand to spin up after power up and IDENTIFY DEVICE response is incomplete C837 Device does not requires SET FEATURES subcommand to spin up after power up and IDENTIFY DEVICE response is complete All other valies Reserved Power up in Standby feature set is not supported The value for this WORD is C837h WORD 3 Logical head number that user can access in default mode 2 WORD ...

Page 85: ... 5 minutes or more The value for this WORD is 4000h WORD 51 PIO data transfer cycle timing mode bit 15 8 PIO data transfer cycle timing mode bit 7 0 Reserved The value returned in Bits 15 8 should fall into one of the mode 0 through mode Note For backwards compatibility with BIOS written before Word 64 was defined for advanced modes a device reports in Word 51 the highest original PIO mode i e PIO...

Page 86: ...can access in LBA mode bit31 24 by word 61 bit 7 0 bit23 16 by word 61 bit 15 8 bit15 8 by word 60 bit 7 0 bit 7 0 by word 60 bit 15 8 The maximum value that shall be placed in this field is 0FFFFFFFh The power on values for each models are Drive Type 5 Word 60 61 MK3006GAL 58 605 120 037E3E40H MK4006GAH 78 126 048 04A81BE0H MK6006GAH 117 210 240 06FC7C80H WORD 62 Reserved WORD 63 Mode information...

Page 87: ... WORD 69 79 Reserved WORD 80 Major version number If not 0000h or FFFFh the device claims compliance with the major version s as indicated by bits 1 6 being equal to one Values other than 0000h and FFFFh are bit significant Since the ATA standards maintain downward compatibility a device may set more than one bit WORD 81 Minor version number If an implementor claims that the revision of the standa...

Page 88: ...mand supported The value for this WORD is 7D09h WORD 84 Features Command sets supported bit 15 0 Fixed bit 14 1 Fixed bit 13 1 Fixed bit 12 6 Reserved bit 5 1 General Purpose Logging feature set supported bit 4 Reserved bit 3 1 Media Card Pass Through command feature set supported bit 2 1 Media serial number supported bit 1 1 SMART self test supported bit 0 1 SMART error logging supported The valu...

Page 89: ...e for this WORD is 3C09h WORD 87 Features Command sets enabled bit 15 0 Fixed bit 14 1 Fixed bit 13 1 Fixed bit 12 6 Reserved bit 5 1 General Purpose Logging feature set supported bit 4 Reserved bit 3 1 Media Card Pass Through command feature set enabled bit 2 1 Media serial number is valid bit 1 1 SMART self test supported bit 0 1 SMART error logging supported The value for this WORD is 6023h WOR...

Page 90: ...e number 00 Reserved 01 a jumper was used 10 the CSEL signal was used 11 some other method was used or the method is unknown 8 1 Fixed bit 7 0 Device 0 hardware reset result Device 1 shall clear these bit to zero Device 0 shall set these bills as follows 7 Reserved 6 0 Device 0 does not respond when Device 1 is selected 1 Device 0 responds when Device 1 is selected 5 0 Device 0 did not detect the ...

Page 91: ...Toshiba Corporation Digital Media Network Company Page 91 of 157 2005 Copyright TOSHIBA Corporation All Rights Reserved This function is not supported The value for this WORD is 0000h ...

Page 92: ... the security is enabled bit 0 security supported 1 security is supported WORD 129 159 Reserved WORD 160 CFA power mode bit 15 Word 160 supported bit 14 Reserved bit 13 CFA power mode 1 is required for one or more commands implemented by the device bit 12 CFA power mode 1 disabled bit 11 0 Maximum current in ma This function is not supported The value for this WORD is 0000h WORD 161 175 Reserved W...

Page 93: ...cate the maximum address that can be accessed In CHS mode the value of Read Native Max Address command should be set in HD SN register Otherwise the value shall be ignored and the value of Read Max Address command will be used If an LBA bit DRV HD register bit 6 is set the value in LBA mode shall be set If the address exceeding the set value is accessed ABORT ERROR error will be reported This set ...

Page 94: ...til the next power cycle When the device accepts this command the device is in Set_Max_Unlocked state Table 10 8 7 SET MAX SET PASSWORD data content Word Content 0 Reserved 1 16 Password 32 bytes 17 255 Reserved 10 8 31 3 Set Max Lock F9h with the content of the Features register equal to 02h COMMAND CODE 1 1 1 1 1 0 0 1 REGISTER REGISTER SETTING NORMAL COMPLETION DR DRIVE No no change CY no chang...

Page 95: ...er is set to a value of five and shall be decremented for each password mismatch when SET MAX UNLOCK is issued and the device is locked When this counter reaches zero then the SET MAX UNLOCK command shall return command aborted until a power cycle If the password compare matches then the device shall make a transition to the Set_Max_Unlocked state and all SET MAX commands shall be accepted 10 8 31...

Page 96: ...ommand Otherwise it will be terminated with ABORT ERROR If this command is issued twice with a volatile bit set to 1 after power up or hardware reset ID Not Found error will be reported If a host protected area has been established by a SET MAX ADDRESS command this command will be terminated with ABORT ERROR Volatile bit SC register bit 0 If this command is issued with a volatile bit set to 1 the ...

Page 97: ...ETTING NORMAL COMPLETION DR drive no no change LBA Low Current Previous HOB 0 HOB 1 Max LBA 7 0 Max LBA 31 24 LBA Mid Current Previous HOB 0 HOB 1 Max LBA 15 8 Max LBA 39 32 LBA High Current Previous HOB 0 HOB 1 Max LBA 23 16 Max LBA 47 40 SC Current Previous HOB 0 HOB 1 no change no change FT Current Previous reserved reserved HOB 0 HOB 1 no change no change This command sets the maximum address ...

Page 98: ...s show mode figure PIO default transfer mode 00000 000 PIO default transfer mode disable IORDY 00000 001 PIO flow control transfer mode nnn 00001 nnn Multiword DMA mode nnn 00100 nnn Ultra DMA mode nnn 01000 nnn Reserved 10000 nnn PIO default mode is mode 4 flow control DMA default mode is Multiword DMA mode 2 The level of Advanced Power Management function is set in Sector count register C0h FEh ...

Page 99: ...lid if word 0 bit 0 1 18 255 Reserved The settings of the identifier and security level bits interact as shown in the table below Identifier and security level Identifier Level Command result User High The password supplied with the command will be saved as the new user password The lock function will be enabled by the next power on The drive can then be unlocked by either the user password or the...

Page 100: ...K command will be rejected If the Identifier bit is set to user the drive compares the supplied password with the stored user password If the drive fails in comparing passwords then the drive returns an abort error to the host and decrements the unlock counter This counter is initially set to five and will be decremented for each mismatched passwords when SECURITY UNLOCK is issued and the drive is...

Page 101: ...RE command must be completed immediately prior to the SECURITY ERASE UNIT command otherwise the SECURITY ERASE UNIT command shall be aborted This command disables the drive lock function however the master password is still stored internally within the drive and may be reactivated later when a new user password is set 10 8 40 SECURITY FREEZE LOCK F5h COMMAND CODE 1 1 1 1 0 1 0 1 REGISTER REGISTER ...

Page 102: ...ssword match the given password the drive disables the lock function This command does not change the Master password which may be reactivated later by setting a user password Security Disable Information Word Content 0 Control word Bit 15 1 Reserved Bit 0 Identifier 0 compare user password 1 compare master password 1 16 Password 32 bytes 17 255 Reserved 10 8 42 SMART Function Set B0h This command...

Page 103: ...Byte Description 0 1 Data structure revision number 2 361 1st 30th Individual attribute data 362 Off line data collection status 363 Self test execution status 364 365 Total time in seconds to complete off line data collection activity 366 Reserved 367 Off line data collection capability 368 369 SMART capability 370 Error logging capability 7 1 Reserved 0 1 Device error logging supported 371 Self ...

Page 104: ...Preserving Attribute bit bit 6 15 Reserved 3 Attribute value 01h FDh 1 00h FEh FFh Not in use 01h Minimum value 64h Initial value Fdh Maximum value 4 Worst Ever normalized Attribute Value valid values from 01h FEh 5 10 Raw Attribute Value Attribute specific raw data FFFFFFh reserved as saturated value 11 Reserved 00h 1 For ID 199 CRC Error Count Initial value C8h ID Attribute Name 0 Indicates that...

Page 105: ...through 9 A value of 0 indicates the self test routine is complete A value of 9 indicates 90 of total test time remaining Bits 4 7 Self test Execution Status The value in these bits indicates the current Self test Execution Status Self test execution status values Value Description 0 The previous self test routine completed without error or no self test has ever been run 1 The self test routine wa...

Page 106: ... set to one the device implements the Short and Extended self test routines This bit is set to 1 bits 5 reserved This bit is set to 0 bits 6 Selective self test implemented bit If this bit is cleared to zero the device does not implement the Selective self test routine If this bit is set to one the device implements the Selective self test routine This bit is set to 1 bits 7 reserved This bit is s...

Page 107: ...DRQ resets BSY and issues an interrupt to report to the host that data transfer is ready Byte Descriptions 0 1 Data structure revision number 2 361 1st 30th Individual attribute threshold data 362 510 Reserved 511 Data structure checksum BYTE 0 1 Data structure revision number The value for this byte is 0010h BYTE 2 361 Individual attribute threshold data Individual attribute threshold data consis...

Page 108: ...register before issuing this command may disable this function Disabling this feature does not preclude the drive from saving attribute values to the attribute data sector during other normal save operations A value of F1h written by the host into the drive s Sector Count register before issuing this command will cause this function to be enabled Any other non zero value written by the host into t...

Page 109: ... in captive mode 131 Reserved 132 Execute SMART Selective self test routine immediately in captive mode 133 255 Reserved 10 8 42 5 1 Off line mode The following describes the protocol for executing a SMART EXECUTE OFF LINE IMMEDIATE subcommand routine including a self test routine in the off line mode a The device executes command completion before executing the subcommand routine b After clearing...

Page 110: ...hile a device is performing the routine the device may discontinue its testing place the results of this routine in the Self test execution status byte and complete the command 10 8 42 5 3 SMART off line routine This routine will only be performed in the off line mode The results of this routine are placed in the Off line data collection status byte 10 8 42 5 4 SMART Short self test routine Depend...

Page 111: ...n If the device is powered down before the off line scan is completed the off line scan shall resume when the device is again powered up From power up the resumption of the scan shall be delayed the time indicated in the Selective self test pending time field in the Selective self test log During this delay time the pending flag shall be set to one and the active flag shall be set to zero in the S...

Page 112: ...rror log RO 03h Extended comprehensive SMART error log See Note 04h 05h Reserved RO 06h SMART self test log RO 07h Extended SMART self test log See Note 08h Reserved RO 09h Selective self test log RO 0Ah 7Fh Reserved RO 80h 9Fh Host vendor specific R W A0h FFh Reserved VS Key RO Log is read only by the host R W Log is read or written by the host VS Log is vendor specific thus read write ability is...

Page 113: ... The value of the SMART error log version byte is set to 01h 10 8 42 6 2 2 Error log data structure An error log data structure will be presented for each of the last five errors reported by the device These error log data structure entries are viewed as a circular buffer That is the first error will create the first error log data structure the second error the second error log structure etc The ...

Page 114: ... from reporting the commands that preceded the command for which the error is being reported or that preceded a reset In this case the command data structures are zero filled If the command data structure represents a command or software reset the content of the command data structure will be as shown in the following Table Command data structure Byte Descriptions n Content of the Device Control r...

Page 115: ... error information will be vendor specific State will contain a value indicating the state of the device when command was written to the Command register or the reset occurred as described in the following Table State field values Value State x0h Unknown x1h Sleep x2h Standby x3h Active Idle with BSY cleared to zero x4h Executing SMART off line or self test x5h xAh Reserved xBh xFh Vendor unique T...

Page 116: ...ror log data structures shall not include errors attributed to the receipt of faulty commands such as command codes not supported by the device or requests with invalid parameters or invalid addresses Comprehensive error log Byte First sector Subsequent sectors 0 SMART error log version Reserved 1 Error log index Reserved 2 91 First error log data structure Data structure 5n 1 92 181 Second error ...

Page 117: ...f test log sector The following Table defines the 512 bytes that make up the SMART self test log sector Self test log data structure Byte Descriptions 0 1 Self test log data structure revision number 2 25 First descriptor entry 26 49 Second descriptor entry 482 505 Twenty first descriptor entry 506 507 Vendor specific 508 Self test index 509 510 Reserved 511 Data structure checksum 10 8 42 6 4 1 S...

Page 118: ... was issued Content of the self test execution status byte will be the content of the self test execution status byte when the nth self test was completed Life timestamp will contain the power on lifetime of the device in hours when the nth self test subcommand was completed Content of the self test failure checkpoint byte will be the content of the self test failure checkpoint byte when the nth s...

Page 119: ...test Read 502 503 Feature flags R W 504 507 Vendor specific Vendor specific 508 509 Selective self test pending time R W 510 Reserved Reserved 511 Data structure checksum R W 10 8 42 6 5 1 Data structure revision number The value of the data structure revision number filed shall be 01h This value shall be written by the host and returned unmodified by the device 10 8 42 6 5 2 Test span definition ...

Page 120: ...When set to one perform off line scan after selective test 2 Vendor specific 3 When set to one off line scan after selective test is pending 4 When set to one off line scan after selective test is active 5 15 Reserved Bit 1 shall be written by the host and returned unmodified by the device Bits 4 3 shall be written as zeros by the host and the device shall modify them as the test progresses 10 8 4...

Page 121: ...1 1 0 0 0 0 REGISTER REGISTER SETTING NORMAL COMPLETION DR DRIVE No no change CY C24Fh no change HD no change SN no change SC no change FT D8h no change This command enables access to all SMART capabilities of the drive Prior to receipt of this command Parameters for drive failure prediction are neither monitored nor saved by the drive The state of SMART either enabled or disabled will be preserve...

Page 122: ...e sets BSY disables SMART capabilities and functions clears BSY and asserts INTRQ After receipt of this command by the drive all other SMART commands except for SMART ENABLE OPERATIONS are disabled and invalid and will be aborted by the drive including SMART DISABLE OPERATIONS commands with an Aborted command error 10 8 42 10 SMART Return Status COMMAND CODE 1 0 1 1 0 0 0 0 REGISTER REGISTER SETTI...

Page 123: ...ically initiate or resume performance of its off line data collection activities or this command may cause the automatic off line data collection feature to be disabled A value of zero written by the host into the device s Sector Count register before issuing this subcommand will cause the feature to be disabled Disabling this feature does not preclude the device from saving attribute values to no...

Page 124: ...the number of sectors to be read from the specified log The log transferred by the drive shall start at the sector in the specified log at the specified offset regardless of the sector count requested LBA Low Specifies the log to be returned as described in the following Table LBA Mid Specifies the first sector of the log to be read Log Sector Log sector address Content R W 00h Log directory RO 01...

Page 125: ...rror log is 64 sectors Error log data structures shall include UNC errors IDNF errors for which the address requested was valid servo errors write fault errors etc Error log data structures shall not include errors attributed to the receipt of faulty commands such as command codes not implemented by the device or requests with invalid parameters or invalid addresses All 28 bit entries contained in...

Page 126: ...ucture n 54 thru n 71 Fourth command data structure n 72 thru n 89 Fifth command data structure n 90 thru n 123 Error data structure 10 8 43 2 3 1 Command data structure The fifth command data structure shall contain the command or reset for which the error is being reported The fourth command data structure should contain the command or reset that preceded the command or reset for which the error...

Page 127: ...l be the time since power on in milliseconds when command acceptance occurred This timestamp may wrap around 10 8 43 2 3 2 Error data structure The error data structure shall contain the error description of the command for which an error was reported as described in the following table If the error was logged for a hardware reset the content of bytes n 1 through n 11 shall be vendor specific and ...

Page 128: ...ommand or reset for which the error is being reported was received when the device was in the process of executing a SMART off line or self test Life timestamp shall contain the power on lifetime of the device in hours when command completion occurred 10 8 43 2 4 Device error count The device error count field shall contain the total number of errors attributable to the device that have been repor...

Page 129: ...y 18n 1 30 55 Descriptor entry 2 Descriptor entry 18n 2 472 497 Descriptor entry 18 Descriptor entry 18n 18 498 499 Vendor specific Vendor specific 500 510 Reserved Reserved 511 Data structure checksum Data structure checksum n is the sector number within the log The first sector is sector zero This log is viewed as a circular buffer The first entry will begin at byte 4 the second entry will begin...

Page 130: ... the self test execution status byte shall be the content of the self test execution status byte when the nth self test was completed see 10 8 42 5 Life timestamp shall contain the power on lifetime of the device in hours when the nth self test subcommand was completed Content of the self test failure checkpoint byte may contain additional information about the self test that failed The failing LB...

Page 131: ...B 0 HOB 1 Reserved Reserved LBA Mid Current Previous Sector offset 7 0 Sector offset 15 8 HOB 0 HOB 1 Reserved Reserved LBA High Current Previous Reserved Reserved HOB 0 HOB 1 Reserved Reserved SC Current Previous sector count 7 0 sector count 15 8 HOB 0 HOB 1 Reserved Reserved FT Current Previous Reserved Reserved HOB 0 HOB 1 no change no change This command writes a specified number of 512 byte ...

Page 132: ...by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command response to the original settings as indicated by the data returned from the execution of a DEVICE CONFIGURATION IDENTIFY command 10 8 45 2 Device Configuration Freeze Lock COMMAND CODE 1 0 1 1 0 0 0 1 REGISTER REGISTER SETTING NORMAL COMPLETION DR DRIVE No no change CY na no chan...

Page 133: ... data structure via PIO data in transfer The content of this data structure indicates the selectable commands modes and feature sets that the device is capable of supporting If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities the response to an IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command will reflect the reduced set of capabilities while the DEVICE CONFIGURATION I...

Page 134: ... in Standby feature set supported 3 1 Security feature set supported 2 1 SMART error log supported 1 1 SMART self test supported 0 1 SMART feature set supported 8 254 Reserved 255 Integrity word 15 8 Checksum 7 0 Signature 10 8 45 3 1 1 Word 0 Data structure revision Word 0 shall contain the value 0001h 10 8 45 3 1 2 Word 1 Multiword DMA modes supported Word 2 bits 2 0 contain the same information...

Page 135: ...indicates that the device is capable of supporting the Automatic Acoustic Management feature set Word 7 bit 7 if set to one indicates that the device is capable of supporting the Host Protected Area feature set Word 7 bit 8 if set to one indicates that the device is capable of supporting the 48 bit Addressing feature set Word 7 bits 9 through 15 are reserved 10 8 45 3 1 6 Words 8 254 Reserved 10 8...

Page 136: ...mode or feature that cannot be changed If not the value shall be 00h Cylinder High If the command was aborted because an attempt was made to modify a bit that cannot be modified with the device in its current state this register shall contain the offset of the first word encountered that cannot be changed If an illegal maximum LBA address is encountered the offset of word 3 shall be entered If a c...

Page 137: ...ess 7 Command set feature set supported 15 9 Reserved 8 1 48 bit Addressing feature set supported 7 1 Host Protected Area feature set supported 6 1 Automatic acoustic management supported 5 1 READ WRITE DMA QUEUED commands supported 4 1 Power up in Standby feature set supported 3 1 Security feature set supported 2 1 SMART error log supported 1 1 SMART self test supported 0 1 SMART feature set supp...

Page 138: ... mode 5 4 3 2 or 1 is supported or if Ultra DMA mode 5 4 3 2 1 or 0 is selected 10 8 45 4 2 4 Words 3 6 Maximum LBA address Words 3 through 6 define the maximum LBA address This shall be the highest address accepted by the device after execution of the command When this value is changed the content of IDENTIFY DEVICE words 60 61 100 101 102 and103 shall be changed as described in the SET MAX ADDRE...

Page 139: ... DEVICE response Word 7 bit 1 is cleared to disable support for the SMART self test and has the effect of clearing bit 1 in words 84 and 87 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response Word 7 bit 0 is cleared to disable support for the SMART feature set and has the effect of clearing bit 0 in words 82 and 85 of the IDENTIFY DEVICE or IDENTIFY PACKET DEVICE response If bits 1 and 2 of ...

Page 140: ...ITY DISABLE PASSWORD Parameter word for the Security mode feature set is described in IDENTIFY DEVICE response Word 128 10 9 1 Security mode default setting The drive is shipped with the master password set to 20h value ASCII blanks and the lock function disabled The system manufacturer dealer may set a new master password by using the SECURITY SET PASSWORD command without enabling the lock functi...

Page 141: ...ss commands until a SECURITY UNLOCK command is successfully completed Power on Locked mode UNLOCK ERASE Media access Non media PREPARE access No Password ERASE Reject match UNIT Command Execute Command Yes Unit erased Unlock mode Lock function disabled Normal operation all commands are available FREEZE LOCK Normal operation Frozen mode commands are available Figure 5 Password set security mode pow...

Page 142: ... the user password is lost and Maximum security level is set it is impossible to access data However the drive can be unlocked using the ERASE UNIT command with the master password The drive will erase all user data and unlock the drive User password lost High Level UNLOCK with master password Maximum ERASE PREPARE Normal operation ERASE UNIT with master password Normal operation but data lost Fig...

Page 143: ... O O O INITIALIZE DEVICE PARAMETERS O O O NOP O O O READ BUFFER O O O READ DMA EXT X O O READ MULTIPLE EXT X O O READ NATIVE MAX ADDRESS EXT O O O READ SECTORS EXT X O O READ SENSE DATA O O O READ VERIFY EXT X O O RECALIBRATE O O O SECURITY DISABLE PASSWORD X O X SECURITY ERASE PREPARE O O O SECURITY ERASE UNIT O O X SECURITY FREEZE LOCK X O O SECURITY SET PASSWORD X O X SECURITY UNLOCK O O X SEEK...

Page 144: ... this feature set are SMART READ ATTRIBUTE VALUES SMART READ ATTRIBUTE THRESHOLDS SMART ENABLE DISABLE ATTRIBUTE AUTOSAVE SMART SAVE ATTRIBUTE VALUE SMART EXECUTE OFF LINE IMMEDIATE SMART READ LOG SECTOR SMART WRITE LOG SECTOR SMART ENABLE OPERATIONS SMART DISABLE OPERATIONS SMART RETURN STATUS SMART ENABLE DISABLE AUTOMATIC OFF LINE 10 10 1 Attributes Attributes are the specific performance or ca...

Page 145: ... Some of electric circuit and servo functions are powered off in this mode The heads are stopped near the disk center If a shock is detected by Shock Sensor the drive enters into Performance Idle mode automatically Power consumption for Active Idle mode is 55 65 lower than that of Performance Idle mode Command processing time is approximately 35ms longer than that of Performance Idle mode 10 11 3 ...

Page 146: ...ex for the Task File registers are as follows Table 10 12 1 Initialization of Task File registers REGISTER POWER ON HARDWARE RESET SOFTWARE RESET Data 00 00 00 Error 01 01 01 Sector Count 01 01 01 Sector Number 01 01 01 Cylinder Low 00 00 00 Cylinder High 00 00 00 Device Head Register 00 00 00 Status Alternate Status 50 or 52 50 or 52 50 or 52 Device address9 7E or FE 7E or FE 7E or FE ECC Length ...

Page 147: ...e runs as Drive1 when the jumper plug is inserted into position C D or if jumper plug is set to position B D when P28 CSEL signal is high In case of two drive configuration one shall be Drive0 and the other should be Drive1 ATA ATAPI specifies to use P28 with jumper plug set to position B D It is recommended to follow the ATA ATAPI specification Jumper P28 Drive No Jumper Drive0 C D Jumper Drive1 ...

Page 148: ...he data in the write buffer are written on the media 10 14 2 Notes for write cache 1 Loss of data in write buffer If write cache is enabled hard reset or soft reset does not cause data loss But power off immediate after completion of the command may cause data loss because actual writing of the data onto the media is not completed at this moment Therefore it is recommended that any other command e...

Page 149: ...ared when host reads Status register issues a reset or writes to the Command register Interrupts are not cleared when host reads Alternate Status register A command shall only be interrupted with a hardware or software reset The result of writing to the command register while BSY 1 or DRQ 1 is unpredictable and may result in data corruption Therefore a command should only be interrupted by a reset...

Page 150: ...ector or block of data via the Data register 6 In response to a sector or block of data being transferred the drive clears the DRQ bit The Read Multiple command transfers one block the number of sectors defined by the Set Multiple command of data for each interrupt The other commands transfer one sector of data for each interrupt If the drive detects an invalid parameter in register setting the dr...

Page 151: ...ter 3 After receiving the sector or block the drive clears the DRQ bit and sets the BSY bit 4 When the drive has finished processing the sector or block it sets the DRQ bit and clears the BSY bit and asserts INTRQ 5 After detecting INTRQ the host reads the Status register 6 The drive negates INTRQ in response to the Status register being read The drive negates INTRQ in response to the Status regis...

Page 152: ...ART Enable Operation SMART Disable Operation SMART Return Status SMART Enable Disable Automatic Off line SET MAX ADDRESS SET MAX ADDRESS EXT SET MAX LOCK SET MAX UNLOCK SET MAX FREEZE LOCK DEVICE CONFIGRATION RESTORE DEVICE CONFIGRATION FREEZE LOCK DEVICE CONFIGRATION SET READ SENCE DATA Non data protocol a The host writes any required command parameters to the Features Sector Count Sector Number ...

Page 153: ... The interrupt handler for DMA transfers is different in that no intermediate sector interrupts are issued on multi sector transfer but issued only once at the completion of each command DMA data transfer protocol a Host initializes the DMA channel b Host writes any required command parameters to the Features Sector Count Sector Number Cylinder High Cylinder Low and Device Head registers c Host wr...

Page 154: ...Q c A host indicates it is ready to initiate the requested Ultra DMA burst by asserting DMACK d A host shall never assert DMACK without first detecting that DMARQ is asserted e For Ultra DMA data in bursts a drive may begin driving DD 15 0 after detecting that DMACK is asserted STOP negated and HDMARDY is asserted f After asserting DMARQ or asserting DDMARDY for an Ultra DMA data out burst the sha...

Page 155: ...o the asserted state No data shall be transferred on this transition of STROBE g A sender returns STROBE to the asserted state whenever it detects a termination request from the recipient No data shall be transferred nor CRC calculated on this edge of DSTROBE h Once a recipient requests a termination it does not change DMARDY from the negated state for the remainder of an Ultra DMA burst k A recip...

Page 156: ... f9 XOR f14 CRCIN15 f1 XOR f6 XOR f13 f1 DD0 XOR CRCOUT15 f9 DD8 XOR CRCOUT7 XOR f5 f2 DD1 XOR CRCOUT14 f10 DD9 XOR CRCOUT6 XOR f6 f3 DD2 XOR CRCOUT13 f11 DD10 XOR CRCOUT5 XOR f7 f4 DD3 XOR CRCOUT12 f12 DD11 XOR CRCOUT4 XOR f1 XOR f8 f5 DD4 XOR CRCOUT11 XOR f1 f13 DD12 XOR CRCOUT3 XOR f2 XOR f9 f6 DD5 XOR CRCOUT10 XOR f2 f14 DD13 XOR CRCOUT2 XOR f3 XOR f10 f7 DD6 XOR CRCOUT9 XOR f3 f15 DD14 XOR CR...

Page 157: ...TRQ set When the drive is in idle mode 20 sec maximum From BSY 1 to BSY 0 DRQ 1 INTRQ set When the drive is in standby mode 35 sec maximum Drive Busy during data transfer 5 µs minimum DATA OUT COMMANDS From writing to command register to BSY 1 400 ns maximum From BSY 1 to BSY 0 DRQ 1 700 µs 1 maximum Drive Busy during data transfer 5 µs minimum From BSY 1 to INTRQ set When the drive is in idle mod...

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