Toshiba 29VH27E, Service Manual

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14
29 VRD/BCS IN X DAC Reference, Beam Current Safety
30 FBLIN1 IN GNDO Fast-Blank1 Input
31 RIN1 IN GNDO Analog Red1 Input
32 GIN1 IN GNDO Analog Green1 Input
33 BIN1 IN GNDO Analog Blue1 Input
34 FBLIN2 IN GNDO Fast-Blank2 Input
35 RIN2 IN GNDO Analog Red2 Input
36 GIN2 IN GNDO Analog Green2 Input
37 BIN2 IN GNDO Analog Blue2 Input
38 TEST IN GNDD Test Pin
39 RESQ IN X Reset Input, active low
40 PWM1 OUT LV I
2
C-controlled DAC
41 PWM2 OUT LV I
2
C-controlled DAC
42 HCS IN GNDD Half-contrast
43 C0 IN GNDD Picture Bas Chroma (LSB)
44 C1 IN GNDD Picture Bas Chroma
45 C2 IN GNDD Picture Bas Chroma
46 C3 IN GNDD Picture Bas Chroma
47 C4 IN GNDD Picture Bas Chroma
48 C5 IN GNDD Picture Bas Chroma
49 C6 IN GNDD Picture Bas Chroma
50 C7 IN GNDD Picture Bas Chroma (MSB)
51 VSUPD SUPPLY X Supply Voltage, Digital Circuitry
52 GNDD SUPPLY X Ground, Digital Circuitry
53 LLC2 IN X System Clock Input (27/32/40.5 MHz)
54 Y0 IN GNDD Picture Bas Luma (LSB)
55 Y1 IN GNDD Picture Bas Luma
56 Y2 IN GNDD Picture Bas Luma
57 Y3 IN GNDD Picture Bas Luma
58 Y4 IN GNDD Picture Bas Luma
59 Y5 IN GNDD Picture Bas Luma
60 Y6 IN GNDD Picture Bas Luma
61 Y7 IN GNDD Picture Bas Luma (MSB)
62 LLC1 IN VSUPD Single Line-Locked Clock Input (13.5/16 MHz)
63 HS IN X Horizontal Sync Input
64 VS IN GNDD Vertical Sync Input
65 XTALK2 OUT X Analog Crystal Output (5-MHz Security Clock)
66 XTALK1 IN X Analog Crystal Input (5-MHz Security Clock)
67 SDA IN/OUT X I
2
C-Bus Data
68 SCL IN/OUT X I
2
C-Bus Clock
14.9.SDA5550
14.9.1.General definition
The SDA5550M is a single chip teletext decoder for decoding World System Teletext data as well as
Video Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling
(WSS) data used for PAL plus transmissions (Line 23). The device provides an integrated general-
purpose, fully 8051-compatible Microcontroller with television specific hardware features.
Microcontroller has been enhanced to provide powerful features such as memory banking, data
pointers, and additional interrupts etc. The on-chip display unit for displaying Level 1.5 teletext data can
also be used for customer defined on screen displays. Internal XRAM consists of up to 17 Kbytes. This
device can support external memory up to 1Mbyte ROM and RAM.TVTEXT Controller contains a data
slicer for VPS, WSS, PDC and TXT, an acceleration acquisition hardware module, a display generator
for Level 1.5 TXT and powerful On screen Display capabilities based on parallel attributes, and pixel
oriented characters (DRCS). The 8 bit Microcontroller operates at 360nsec cycle time (min). Controller
with dedicated hardware does most of the internal TXT acquisition processing, transfer data to/from
external memory interface and receives/transmits data via I
2
C-firmware user interface. SDA5550M is
realized in 0.25 micron technology with 2.5V supply voltage and 3.3V I/O compatible. The IC produces
the following input or output control signals; AGC_CON, MODE_SW, L / L’, PIP_MODS, PIP_SEL,
ON/OFF (stand-by), SC1..3_IN_AV (pin 8 information from 3 SCARTs), AFC, MUTE (to mute audio
output IC), I
2
CEN.