TOPSCCC Technology EX-93211, User Manual

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EX-93211/93511/93711/93911User Manual 39
3.1.3 Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected. The default is By SPD.
CAS Latency Time
You can select CAS latency time in HCLKs of 2/2 or 2.5 or 3/3. The system board designer should set
the values in this field, depending on the DRAM installed. Do not change the values in this field unless
you change specifications of the installed DRAM or the installed CPU. The choices are 2 and 3.
Active to Precharge Delay
The default setting for the Active to Precharge Delay is 6.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address Strobe) and CAS (Column
Address Strobe) signals. This delay occurs when the SDRAM is written to, read from or refreshed.
Reducing the delay improves the performance of the SDRAM.