P440 Data Sheet / User Guide
DRAFT
33
Fig. 18: SPI interconnect signals
The SPI port uses 8-bit bytes sent MSb first. The CLK idle state is high. The data is propagated on
the falling-edge (leading-edge) of clock and sampled on the rising-edge (trailing-edge) of clock as
shown below in
Figure 19
:
CSn
CLK
MOSI
MISO
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
7
Bit 0
0
Fig. 19: Signaling timing diagram
The master drives the SPI chip-select low (CSn in above figure) and shifts an 8-bit command,
possibly followed by data. The first bit (MSb) of a command is always set. If the second bit is set,
then it is a read command, otherwise it is a write command. The commands are listed below in
Figure 20
. The chip-select must stay active-low for the entire transaction, which is required to be on
8-bit boundaries. This and other timing diagrams are shown in
Figure 21.
Timing constraints are
shown in
Figure 22.
Command
Function
Command Format
Response Format
0x80
Write to slave input FIFO
Command
followed by data
N/A
0xC0
Read from slave output
FIFO
Command
Slave output FIFO data
0xC2
Read slave output FIFO
byte count
Command
Two bytes: MSB followed by LSB
Fig. 20: SPI command structure
Master
Slave
CLK
CSn
MOSI
MISO
INT
