Preliminary
THCV245A_Rev.0.90_E
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Table 40.
IC External sub-link operator selectable Error / status signal
6.25 Internal Error / status signal monitoring register
Internal error or status signal can be monitored as register read value.
Error count register can be cleared by particular register write “1” access.
Error status register can be masked to “0” fixed by particular register appropriate write access.
Table 41.
Internal Error / status signal monitoring register
R_SLINK_ERR_SELn[3:0] (n=0,1)
R_EXT_ERR_SELn[3:0] (n=0,1)
Assignment on Sub-Link Master
(MSSEL=0)
Assignment on Sub-Link Slave
(MSSEL=1)
'h00
'h01
'h02
R_SLINK_ERR_SEL0 of Sub-Link Slave
R_SLINK_ERR_SEL0 of Sub-Link Master
'h03
R_SLINK_ERR_SEL1 of Sub-Link Slave
R_SLINK_ERR_SEL1 of Sub-Link Master
'h04
'h05
'h06
'h07
'h08
'h09
'h0A
R_INT_LOCKN
1'b0
'h0B
R_INT_HTPDN
1'b0
'h0C
R_INT_SLAVESIDE
1'b0
'h0D
R_INT_EXTI2C_ACSEND
1'b0
'h0E
1'b0
R_INT_EXTI2CS_BUSCLR
'h0F
1'b0
R_INT_EXTI2CS_NACK
R_INT_SLINK_PROTERR
R_INT_SLINK_TMOUT
R_ERR_SEL1
R_ERR_SEL2
R_INT_EXTERNAL
R_INT_CKSUM_ERR
R_INT_I2C_TMOUT
1'b0
Module
ERR
/ ERR_CNT
CLEAR
MASK/EN/OFF
Main-Link
R_DHNDL_ERR
-
R_DHNDL_INT_MSK
PLL
PLL_SET_NG
-
R_PLL_SET_NG_MSK
MIPI
R_RX_CRC_ERR_CNT[15:0]
R_CRC_ERR_CNT_CLR
-
MIPI
R_RX_ECC_ERR_CRCT_CNT[15:0]
R_ECC_ERR_CRCT_CNT_CLR
-
MIPI
R_RX_ECC_ERR_DBLE_CNT[15:0]
R_ECC_ERR_DBLE_CNT_CLR
-
Sub-Link
R_SLINK_FBETERR_NUM_*[15:0]
R_SLINK_FBETERR_CLR
-
*H:Enable L:Disable, which is defferent polarity from other mask registers
Description
CRC error count by every Line
ECC1bit error count by every Line
ECC2bit error count by every Line
Sub-link Feald BET error count
Main-Link Data Handle error
PLL auto configuration setting error
