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Texas TMS320x2823x, Reference Manual

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eQEP Registers

Table 4. eQEP Control (QEPCTL) Register Field Descriptions (continued)

Bits

Name

Value

Description

6

SEL

Strobe event latch of position counter

0

The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT =
POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the
QSP bit in the QDECCTL register.

1

Clockwise Direction:
Position counter is latched on rising edge of QEPS strobe
Counter Clockwise Direction:
Position counter is latched on falling edge of QEPS strobe

5-4

IEL

Index event latch of position counter (software index marker)

00

Reserved

01

Latches position counter on rising edge of the index signal

10

Latches position counter on falling edge of the index signal

11

Software index marker. Latches the position counter and quadrature direction flag on index
event marker. The position counter is latched to the QPOSILAT register and the direction flag
is latched in the QEPSTS[QDLF] bit. This mode is useful for software index marking.

3

QPEN

Quadrature position counter enable/software reset

0

Reset the eQEP peripheral internal operating flags/read-only registers. Control/configuration
registers are not disturbed by a software reset.

1

eQEP position counter is enabled

2

QCLM

eQEP capture latch mode

0

Latch on position counter read by CPU. Capture timer and capture period values are latched
into QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register.

1

Latch on unit time out. Position counter, capture timer and capture period values are latched
into QPOSLAT, QCTMRLAT and QCPRDLAT registers on unit time out.

1

UTE

eQEP unit timer enable

0

Disable eQEP unit timer

1

Enable unit timer

0

WDE

eQEP watchdog enable

0

Disable the eQEP watchdog timer

1

Enable the eQEP watchdog timer

Figure 23. eQEP Position-compare Control (QPOSCTL) Register

15

14

13

12

11

8

PCSHDW

PCLOAD

PCPOL

PCE

PCSPW

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

7

0

PCSPW

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -

n

= value after reset

Table 5. eQEP Position-compare Control (QPOSCTL) Register Field Descriptions

Bit

Name

Description

15

PCSHDW

Position-compare shadow enable

0

Shadow disabled, load Immediate

1

Shadow enabled

14

PCLOAD

Position-compare shadow load mode

0

Load on QPOSCNT = 0

SPRUG05A – August 2008 – Revised December 2008

Enhanced QEP (eQEP) Module

31

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Summary of Contents for TMS320x2823x

Page 1: ...TMS320x2833x 2823x Enhanced Quadrature Encoder Pulse eQEP Module Reference Guide Literature Number SPRUG05A August 2008 Revised December 2008 ...

Page 2: ...2 SPRUG05A August 2008 Revised December 2008 Submit Documentation Feedback ...

Page 3: ...3 3 Position Compare Sync Output 17 4 Position Counter and Control Unit PCCU 17 4 1 Position Counter Operating Modes 17 4 2 Position Counter Latch 20 4 3 Position Counter Initialization 22 4 4 eQEP Position compare Unit 22 5 eQEP Edge Capture Unit 24 6 eQEP Watchdog 27 7 Unit Timer Base 27 8 eQEP Interrupt Structure 28 9 eQEP Registers 28 SPRUG05A August 2008 Revised December 2008 Table of Content...

Page 4: ...ECCTL Register 29 22 eQEP Control QEPCTL Register 30 23 eQEP Position compare Control QPOSCTL Register 31 24 eQEP Capture Control QCAPCTL Register 32 25 eQEP Position Counter QPOSCNT Register 33 26 eQEP Position Counter Initialization QPOSINIT Register 33 27 eQEP Maximum Position Count Register QPOSMAX Register 33 28 eQEP Position compare QPOSCMP Register 33 29 eQEP Index Position Latch QPOSILAT R...

Page 5: ...eQEP Position Counter Latch QPOSLAT Register Field Descriptions 34 14 eQEP Unit Timer QUTMR Register Field Descriptions 35 15 eQEP Unit Period QUPRD Register Field Descriptions 35 16 eQEP Watchdog Timer QWDTMR Register Field Descriptions 35 17 eQEP Watchdog Period QWDPRD Register Field Description 36 18 eQEP Interrupt Enable QEINT Register Field Descriptions 36 19 eQEP Interrupt Flag QFLG Register...

Page 6: ...e Data Manual and Errata SPRS439 TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 Digital Signal Controllers DSCs Data Manual contains the pinout signal descriptions as well as electrical and timing specifications for the F2833x 2823x devices SPRZ272 TMS320F28335 F28334 F28332 TMS320F28235 F28234 F28232 Digital Signal Controllers DSCs Silicon Errata describes the advis...

Page 7: ...trol systems It includes the module description and registers SPRUEU1 TMS320x2833x 2823x Enhanced Controller Area Network eCAN Reference Guide describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments SPRUFZ5 TMS320F2833x 2823x Serial Communication Interface SCI Reference Guide describes the SCI which is a two wire asynchron...

Page 8: ...EPI which can be used to indicate an absolute position Encoder manufacturers identify the index pulse using different terms such as index marker home position and zero reference Figure 1 Optical Encoder Disk To derive direction information the lines on the disk are read out by two different photo elements that look at the disk pattern with a mechanical shift of 1 4 the pitch of a line pair between...

Page 9: ...ortionally with the velocity of the motor For example a 2000 line encoder directly coupled to a motor running at 5000 revolutions per minute rpm results in a frequency of 166 6 KHz so by measuring the frequency of either the QEPA or QEPB output the processor can determine the velocity of the motor Quadrature encoders from different manufacturers come with two forms of index pulse gated index pulse...

Page 10: ...of the position sensor and the unit time period T For example consider a 500 line per revolution quadrature encoder with a velocity calculation rate of 400 Hz When used for position the quadrature encoder gives a four fold increase in resolution in this case 2000 counts per revolution The minimum rotation that can be detected is therefore 0 0005 revolutions which gives a velocity resolution of 12 ...

Page 11: ...es the direction input eQEPI Index or Zero Marker The eQEP encoder uses an index signal to assign an absolute start position from which position information is incrementally encoded using quadrature pulses This pin is connected to the index output of the eQEP encoder to optionally reset the position counter for each revolution This signal can be used to initialize or latch the position counter on ...

Page 12: ... memory locations sizes and reset values Table 1 EQEP Memory Map Size x16 Name Offset shadow Reset Register Description QPOSCNT 0x00 2 0 0x00000000 eQEP Position Counter QPOSINIT 0x02 2 0 0x00000000 eQEP Initialization Position Count QPOSMAX 0x04 2 0 0x00000000 eQEP Maximum Position Count QPOSCMP 0x06 2 1 0x00000000 eQEP Position compare QPOSILAT 0x08 2 0 0x00000000 eQEP Index Position Latch QPOSS...

Page 13: ...gister QCLR 0x1A 1 0 0x0000 eQEP Interrupt Clear Register QFRC 0x1B 1 0 0x0000 eQEP Interrupt Force Register QEPSTS 0x1C 1 0 0x0000 eQEP Status Register QCTMR 0x1D 1 0 0x0000 eQEP Capture Timer QCPRD 0x1E 1 0 0x0000 eQEP Capture Period Register QCTMRLAT 0x1F 1 0 0x0000 eQEP Capture Timer Latch QCPRDLAT 0x20 1 0 0x0000 eQEP Capture Period Latch reserved 0x21 31 0 to 0x3F SPRUG05A August 2008 Revise...

Page 14: ...EPxSOUT EQEPxSIN EQEPxIIN EQEPxBIN EQEPxAIN QDECCTL SWAP QEPSTS QDF EQEPA EQEPB 3 1 Position Counter Input Modes Quadrature Decoder Unit QDU www ti com Figure 5 shows a functional block diagram of the QDU Figure 5 Functional Block Diagram of Decoder Unit Clock and direction input to position counter is selected using QDECCTL QSRC bits based on interface input requirement as follows Quadrature coun...

Page 15: ...n truth table and state machine form Both edges of the QEPA and QEPB signals are sensed to generate count pulses for the position counter Therefore the frequency of the clock generated by the eQEP logic is four times that of each input sequence Figure 7 shows the direction decoding and clock generation from the eQEP input signals Table 2 Quadrature Decoder Truth Table Previous Edge Present Edge QD...

Page 16: ...unt operation QEPA input is fed to the QA input of the quadrature decoder and the QEPB input is fed to the QB input of the quadrature decoder Reverse counting is enabled by setting the SWAP bit in the QDECCTL register This will swap the input to the quadrature decoder thereby reversing the counting direction Some position encoders provide direction and clock outputs instead of quadrature outputs I...

Page 17: ...ion with respect to the known reference An example of this is the quadrature encoder mounted on the motor controlling the print head in the printer Here the position counter is reset by moving the print head to the home position and then position counter provides absolute position information with respect to home position In other systems the position counter is reset on every revolution using ind...

Page 18: ...ared only through software The index event latch configuration QEPCTL IEL bits are ignored in this mode and position counter error flag interrupt flag are generated only in index event reset mode Figure 8 Position Counter Reset by Index Pulse for 1000 Line Encoder QPOSMAX 3999 or 0xF9F If the position counter is equal to QPOSMAX then the position counter is reset to 0 on the next eQEP clock for fo...

Page 19: ...ence and subsequently the position counter value is not reset on an index event rather it is reset based on maximum position as described in Section Section 4 1 2 First index marker is defined as the quadrature edge following the first index edge The eQEP peripheral records the occurrence of the first index marker QEPSTS FIMF and direction on the first index event marker QEPSTS FIDF in QEPSTS regi...

Page 20: ...es when moving in the same direction between the index events The index event latch interrupt flag QFLG IEL is set when the position counter is latched to the QPOSILAT register The index event latch configuration bits QEPCTZ IEL are ignored when QEPCTL PCRM 00 Latch on Rising Edge QEPCTL IEL 01 The position counter value QPOSCNT is latched to the QPOSILAT register on every rising edge of an index ...

Page 21: ... Encoder QEPCTL IEL 1 The position counter value is latched to the QPOSSLAT register on the rising edge of the strobe input by clearing the QEPCTL SEL bit If the QEPCTL SEL bit is set then the position counter value is latched to the QPOSSLAT register on the rising edge of the strobe input for forward direction and on the falling edge of the strobe input for reverse direction as shown in Figure 11...

Page 22: ...ut for reverse direction Software Initialization SWI The position counter can be initialized in software by writing a 1 to the QEPCTL SWI bit This bit is not automatically cleared While the bit is still set if a 1 is written to it again the position counter will be re initialized The eQEP peripheral includes a position compare unit that is used to generate a sync output and or interrupt on a posit...

Page 23: ...hows the layout of the eQEP Position Compare Control Register QPOSCTL and Table 5 describes the QPOSCTL bit fields Figure 13 eQEP Position compare Event Generation Points The pulse stretcher logic in the position compare unit generates a programmable position compare sync pulse output on the position compare match In the event of a new position compare match while a previous position compare pulse...

Page 24: ...ment T between unit position events will be correct if the following conditions are met No more than 65 535 counts have occurred between unit position events No direction change between unit position events The capture unit sets the eQEP overflow error flag QEPSTS COEF in the event of capture timer overflow between unit position events If a direction change occurs between the unit position events ...

Page 25: ...nit Figure 15 eQEP Edge Capture Unit Note The QCAPCTL UPPS prescaler should not be modified dynamically such as switching the unit event prescaler from QCLK 4 to QCLK 8 Doing so may result in undefined behavior The QCAPCTL CPPS prescaler can be modified dynamically such as switching CAPCLK prescaling mode from SYSCLK 4 to SYSCLK 8 only after the capture unit is disabled Figure 16 Unit Position Eve...

Page 26: ...Fixed unit time or inverse of velocity calculation rate X Incremental position movement in unit time X Fixed unit position T Incremental time elapsed for unit position movement t k Time instant k t k 1 Time instant k 1 Unit time T and unit period X are configured using the QUPRD and QCAPCTL UPPS registers Incremental position output and incremental time output is available in the QPOSLAT and QCPRD...

Page 27: ...er If no quadrature clock event is detected until a period match QWDPRD QWDTMR then the watchdog timer will time out and the watchdog interrupt flag will be set QFLG WTO The time out value is programmable through the watchdog period register QWDPRD Figure 18 eQEP Watchdog Timer The eQEP peripheral includes a 32 bit timer QUTMR that is clocked by SYSCLKOUT to generate periodic interrupts for veloci...

Page 28: ...nterrupt control register QEINT is used to enable disable individual interrupt event sources The interrupt flag register QFLG indicates if any interrupt event has been latched and contains the global interrupt flag bit INT An interrupt pulse is generated only to the PIE if any of the interrupt events is enabled the flag bit is 1 and the INT flag bit is 0 The interrupt service routine will need to ...

Page 29: ...on compare sync output 12 SPSEL Sync output pin selection 0 Index pin is used for sync output 1 Strobe pin is used for sync output 11 XCR External clock rate 0 2x resolution Count the rising falling edge 1 1x resolution Count the rising edge only 10 SWAP Swap quadrature clock inputs This swaps the input to the quadrature decoder reversing the counting direction 0 Quadrature clock inputs are not sw...

Page 30: ... Timer is unaffected by emulation suspend 13 12 PCRM Position counter reset mode 00 Position counter reset on an index event 01 Position counter reset on the maximum position 10 Position counter reset on the first index event 11 Position counter reset on a unit time event 11 10 SEI Strobe event initialization of position counter 00 Does nothing action disabled 01 Does nothing action disabled 10 In...

Page 31: ...eset 0 Reset the eQEP peripheral internal operating flags read only registers Control configuration registers are not disturbed by a software reset 1 eQEP position counter is enabled 2 QCLM eQEP capture latch mode 0 Latch on position counter read by CPU Capture timer and capture period values are latched into QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register 1 Latch on unit time ...

Page 32: ...r reset Table 6 eQEP Capture Control QCAPCTL Register Field Descriptions Bits Name Description 15 CEN Enable eQEP capture 0 eQEP capture unit is disabled 1 eQEP capture unit is enabled 14 7 Reserved Always write as 0 6 4 CCPS eQEP capture timer clock prescaler 000 CAPCLK SYSCLKOUT 1 001 CAPCLK SYSCLKOUT 2 010 CAPCLK SYSCLKOUT 4 011 CAPCLK SYSCLKOUT 8 100 CAPCLK SYSCLKOUT 16 101 CAPCLK SYSCLKOUT 32...

Page 33: ... Position Counter Initialization QPOSINIT Register Field Descriptions Bits Name Description 31 0 QPOSINIT This register contains the position value that is used to initialize the position counter based on external strobe or index event The position counter can be initialized through software Figure 27 eQEP Maximum Position Count Register QPOSMAX Register 31 0 QPOSMAX R W 0 LEGEND R W Read Write R ...

Page 34: ... defined by the QEPCTL IEL bits Figure 30 eQEP Strobe Position Latch QPOSSLAT Register 31 0 QPOSSLAT R 0 LEGEND R W Read Write R Read only n value after reset Table 12 eQEP Strobe Position Latch QPOSSLAT Register Field Descriptions Bits Name Description 31 0 QPOSSLAT The position counter value is latched into this register on strobe event as defined by the QEPCTL SEL bits Figure 31 eQEP Position C...

Page 35: ...or unit timer to generate periodic unit time events to latch the eQEP position information at periodic interval and optionally to generate interrupt Figure 34 eQEP Watchdog Timer QWDTMR Register 15 0 QWDTMR R W 0 LEGEND R W Read Write R Read only n value after reset Table 16 eQEP Watchdog Timer QWDTMR Register Field Descriptions Bits Name Description 15 0 QWDTMR This register acts as time base for...

Page 36: ...t enable 0 Interrupt is disabled 1 Interrupt is enabled 10 IEL Index event latch interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 9 SEL Strobe event latch interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 8 PCM Position compare match interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled 7 PCR Position compare ready interrupt enable 0 Interrupt is disabled 1 I...

Page 37: ...L Index event latch interrupt flag 0 No interrupt generated 1 This bit is set after latching the QPOSCNT to QPOSILAT 9 SEL Strobe event latch interrupt flag 0 No interrupt generated 1 This bit is set after latching the QPOSCNT to QPOSSLAT 8 PCM eQEP compare match event interrupt flag 0 No interrupt generated 1 This bit is set on position compare match 7 PCR Position compare ready interrupt flag 0 ...

Page 38: ...O PCU WTO QDC PHE PCE INT R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 20 eQEP Interrupt Clear QCLR Register Field Descriptions Bit Field Value Description 15 12 Reserved Always write as 0s 11 UTO Clear unit time out interrupt flag 0 No effect 1 Clears the interrupt flag 10 IEL Clear index event latch interrupt flag 0 No effect 1 Clear...

Page 39: ...bles further interrupts to be generated if an event flags is set to 1 Figure 39 eQEP Interrupt Force QFRC Register 15 12 11 10 9 8 Reserved UTO IEL SEL PCM R 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 PCR PCO PCU WTO QDC PHE PCE Reserved R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 21 eQEP Interrupt Force QFRC Register Field Descriptions ...

Page 40: ...e as 0 Figure 40 eQEP Status QEPSTS Register 15 8 Reserved R 0 7 6 5 4 3 2 1 0 UPEVNT FIDF QDF QDLF COEF CDEF FIMF PCEF R 0 R 0 R 0 R 0 R W 1 R W 1 R W 1 R 0 LEGEND R W Read Write R Read only n value after reset Table 22 eQEP Status QEPSTS Register Field Descriptions Bit Field Value Description 15 8 Reserved Always write as 0 7 UPEVNT Unit position event flag 0 No unit position event detected 1 Un...

Page 41: ... This bit is not sticky and it is updated for every index event 0 No error occurred during the last index transition 1 Position counter error Figure 41 eQEP Capture Timer QCTMR Register 15 0 QCTMR R W LEGEND R W Read Write R Read only n value after reset Table 23 eQEP Capture Timer QCTMR Register Field Descriptions Bits Name Description 15 0 QCTMR This register provides time base for edge capture ...

Page 42: ...r Figure 44 eQEP Capture Period Latch QCPRDLAT Register 15 0 QCPRDLAT R W LEGEND R W Read Write R Read only n value after reset Table 26 eQEP Capture Period Latch QCPRDLAT Register Field Descriptions Bits Name Description 15 0 QCPRDLAT eQEP capture period value can be latched into this register on two events viz unit timeout event reading the eQEP position counter Enhanced QEP eQEP Module 42 SPRUG...

Page 43: ...usiness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all neces...

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