Printed-Circuit Board Layout Guideline
2.4.3
Helpful hints
1. To observe the taper current as the battery voltage approaches the set regulation voltage, allow the
battery to charge or, if using BAT_Load (PR1010), slowly increase the PS #2 voltage powering
BAT_Load (PR1010). Use VM #2 across BAT and GND to measure the battery voltage seen by the IC.
2. To observe the V
INDPM
function, lower the current limit on PS #1.
3. To observe battery supplement mode, apply a resistive load across SYS and GND that is higher than
the maximum charge current.
3
Printed-Circuit Board Layout Guideline
1. To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND,
must be placed as close as possible to the bq2427x.
2. Place a 4.7-µF input capacitor as close as possible to the PMID pin and PGND pin to make the high-
frequency current loop area as small as possible. Place 1-µF input capacitor GNDs as close as
possible to the respective PMID capacitor GND and PGND pins to minimize the ground difference
between the input and PMID.
3. The local bypass capacitor from SYS for bq24272 (or CS+ for bq24273) to GND must be connected
between the SYS (or CS+) pin and PGND of the IC. The intent is to minimize the current path loop
area from the SW pin through the LC filter and back to the PGND pin.
4. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do
not place components such that routing interrupts power stage currents). All small control signals must
be routed away from the high-current paths.
5. The PCB must have a ground plane (return) connected directly to the return of all components through
vias (two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal
components). It is also recommended to put vias inside the PGND pads for the IC, if possible. A star
ground design approach is typically used to keep circuit block currents isolated (high-power/low-power
small-signal) reducing noise-coupling and ground-bounce issues. A single ground plane for this design
gives good results. With this small layout and a single ground plane, no ground-bounce issue exists.
Having the components segregated minimizes coupling between signals.
6. The high-current charge paths into IN, BAT, SYS (or CS+), and from the SW pins must be sized
appropriately for the maximum charge current in order to avoid voltage drops in these traces. The
PGND pins must be connected to the ground plane to return current through the internal low-side FET.
7. For high-current applications, the balls for the power paths must be connected to as much copper in
the board as possible. This allows better thermal performance because the board conducts heat away
from the IC.
13
SLUU916 – April 2012
WCSP-Packaged bq24272/273 Evaluation Modules
Copyright © 2012, Texas Instruments Incorporated
