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TUSB1064RNQ EVM Configuration
3
SLLU287 – March 2018
Copyright © 2018, Texas Instruments Incorporated
TUSB1064RNQ Evaluation Module
3
TUSB1064RNQ EVM Configuration
This section provides the configuration options available in the TUSB1064RNQ EVM.
3.1
TUSB1064RNQ EVM Default Configuration
lists the default configuration pins for the TUSB1064 device. Configuration settings may need to
be optimized depending on the amount of loss of each channel in the system. The EVM is configured to
GPIO mode by default. If I2C configuration is desired, JMP7 (I2C_EN) shunt must be changed to shunt
pins 2-3 (VCC).
Table 1. TUSB1064 Configuration Pins
Reference
Designator
JMP Control
Configuration
JMP1
Downstream EQ1
SHUNT on pin 2-4 (R – 20k to GND)
JMP2
Downstream EQ0
SHUNT on pin 2-4 (R – 20k to GND)
JMP3
Downstream SSEQ1
SHUNT on pin 2-4 (R – 20k to GND)
JMP4
Downstream SSEQ0
SHUNT on pin 2-4 (R – 20k to GND)
JMP5
DP EQ1
SHUNT on pin 2-4 (R – 20k to GND)
JMP6
DP EQ0
SHUNT on pin 2-4 (R – 20k to GND)
JMP7
I2C_EN
SHUNT on pin 1-2 (GND)
J1
FLIP
No SHUNT
J2
CTL0
No SHUNT
J3
CTL1
No SHUNT
J4
EN
SHUNT on pin 1-2 (PU)
3.2
TUSB1064 Equalization Control
Equalization (EQ) can be controlled through I2C or pin-strapping (see
). Each TUSB1064 receiver
lane has individual controls for receiver equalization.
and
detail the gain values for each
available combination for downstream, upstream, and all DisplayPort configurations.
Table 2. Configuration Pin Level Definitions
Level
Settings
0
Option 1: Tie 1 k
Ω
5% to GND.
Option 2: Tie directly to GND.
R
Tie 20 k
Ω
5% to GND.
F
Float (leave pin open)
1
Option 1: Tie 1 k
Ω
5% to VCC.
Option 2: Tie directly to VCC.
Table 3. USB 3.1 EQ Settings
USB 3.1 Downstream Facing Ports
USB 3.1 Upstream Facing Ports
EQ1 Pin Level
EQ1 Pin Level
EQ Gain at 5 GHz
(dB)
SSEQ1 Pin
Level
SSEQ1 Pin
Level
EQ Gain at 5 GHz
(dB)
0
0
–3.0
0
0
–1.5
0
R
–0.8
0
R
0.7
0
F
–0.7
0
F
2.2
0
1
2.2
0
1
3.7
R
0
3.3
R
0
4.7
R
R
4.3
R
R
5.8
R
F
5.1
R
F
6.6
R
1
6.0
R
1
7.4
F
0
6.7
F
0
8.1