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TUSB1042EVM Configuration
3
SLLU277 – September 2017
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Copyright © 2017, Texas Instruments Incorporated
TUSB1042 Evaluation Module
2.2
TUSB1042 EQ Control
Each of the TUSB1042 receiver lanes has individual controls for receiver equalization.
Table 2
and
Table 3
detail the gain values for each available combination for downstream, upstream and all
DisplayPort™ configurations.
Table 2. Configuration Pin-Level Definitions
Level
Settings
0
Option 1: Tie 1K
Ω
5% to GND.
Option 2: Tie directly to GND.
R
Tie 20K
Ω
5% to GND.
F
Float (Leave pin open)
1
Option 1: Tie 1K
Ω
5% to V
CC
.
Option 2: Tie directly to V
CC
.
Table 3. USB 3.1 EQ Settings
USB 3.1 Downstream Facing Ports
USB 3.1 Upstream Facing Ports
EQ1 Pin
Level
EQ0 Pin
Level
EQ Gain @ 5 GHz (dB)
SSEQ1 Pin
Level
SSEQ0 Pin
Level
EQ Gain @ 5 GHz (dB)
0
0
0
0
0
0
0
R
1
0
R
1
0
F
2
0
F
2
0
1
3
0
1
3
R
0
4
R
0
4
R
R
5
R
R
5
R
F
6
R
F
6
R
1
7
R
1
7
F
0
8
F
0
8
F
R
9
F
R
9
F
F
10
F
F
10
F
1
11
F
1
11
1
0
12
1
0
12
1
R
13
1
R
13
1
F
14
1
F
14
1
1
15
1
1
15
2.3
Power
The EVM is designed to operate off of the VBUS from a USB host connected via USB Type B J4. No
external power to be applied via J14 unless standalone operation is desired.
If testing DisplayPort only, or if bypassing VBUS power, the EVM must be powered via J14 (5-V, 1-A
input).