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SLWU070D – February 2010 – Revised August 2016
Copyright © 2010–2016, Texas Instruments Incorporated
Appendix A
SLWU070D – February 2010 – Revised August 2016
A.1
LED Definitions
D1: CDC locked to reference
D6: +6V present
D10: USB device powered up
D11: FPGA configured
D7: TR371125 enabled
D3: DAC input data enabled
D12: DAC powered up
D4: DC Offset compensation enabled with blinking
D5: IQ Correction enabled with blinking
A.2
Connector Descriptions
Designator
Description
J1
RF input. Bypasses both LNAs.
J2
RF input to LNA #2. Bypasses LNA #1.
J3
RF input to LNA #1.
J4
TR371125 LO input source
J13
ADC #1 analog input. Positive analog input when T4 is bypassed.
J14
ADC #1 negative analog input when T4 is bypassed.
J16
ADC #2 analog input. Positive analog input when T5 is bypassed.
J17
ADC #2 negative analog input when T5 is bypassed.
J8
External reference for CDCE62005.
J5
Spare output from CDCE62005
J12
Spare output from CDCE62005
J6
DAC5672 output.
J21
LVDS outputs. Mates with TSW1400 LVDS input connector.
J19
CMOS output data.
J22
Test connector.
J9
+6-VDC input power connector.
J7
USB connector.
J18
FPGA JTAG connector.
J15
FPGA PROM programming connector.