Texas Instruments TSW4200, User Manual, Page: 3 / 12

TCXO
CDCE62005
DAC328x
DATA
Data_CLK
FRAME_CLK
DAC_CLK OSTR_CLK
Transformer Output
or Transformer only Output
J24 RF
J27 LO
FPGA CLK
Modulator Reference CLK
TRF3703-xx
TRF3704
Optional TRF3703-xx
or TRF3704 Output
J21 RF
TRF3720
Filter Bypass
J1
J3
+
_
_
+
J11
Ext. CLK
6V Only
J6
Power
Supply
Circuits
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Introduction
1.3 TSW4200-DAC Configuration
Figure 2. DAC3283 EVM Block Diagram
1. The TSW4200-DAC kit is a DAC3283EVM configured as follow:
(a) Power Supply Option: The kit includes a 6-V power supply input to power supply jack J6. For
proper EVM operation and to prevent damage to the EVM, only use a 6-V power supply.
(b) Analog Output Option: The on-board DAC3283 has dual-channel outputs that go through a filter
network and transformer to J3 (Ch. A) and J1 (Ch. B).
(c) Clock Option: The on-board CDCDE62005 provides clocks to all the on-board devices.
(i) The default DAC clock is configured at 614.4 MHz. The DAC interpolation, FPGA clock
(TSW3100 CLK), and the FIFO OSTR clock can be configured based on the data rate, FPGA
configuration, and system requirement. For more information, please refer to the
DAC3283
datasheet.
(ii) The TSW4200-DAC has a clock output at J11 that provides the reference clock for the
CDCE72010 on the TSW4200-ADC at J19. The default reference clock should be configured
as 19.2 MHz.
2. The EVM has the default jumper setting listed on Table 2 .
3. For more details, refer to the DAC3283EVM User’s Guide ( SLAU311 ).
3 SLWU071C – April 2010 – Revised November 2012 TSW4200 Demonstration Kit
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