Texas Instruments TSW4200, User Manual, Page: 4 / 12

CDCE72010
ADS62Pxx
DATA
Data_CLK
J6
J3
+
_
_
+
J19
491.52MHz
VCXO
/2
245.76MHz
Crystal Filter
+
_
Optional Amplifier Path
Optional Ext. CLK
5V Only
J17
Power
Supply
Circuits
Ref. CLK
CLK Input
Transformers Coupled
Input Circuit
Introduction
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Table 2. TSW4200-DAC Default Jumper Setting
Jumper Default Position Purpose
JP22 2-3 CDCE62005 (U4) external reference clock bias
JP19 Shorted Enable TCXO (U7)
JP9 1-2 DAC3283 (U1) TXENABLE
JP20 1-2 CDCE62005 (U4) power down
JP21 1-2 CDCE62005 (U4) reference select
JP13 2-3 TRF3720 (U3) power save
JP17 1-2 (TRF3720) TRF3720 (U3) or TRF3703 (U10) Power Path
1.4 TSW4200-ADC Configuration
Figure 3. ADS62P49 EVM Block Diagram
1. TSW4200-ADC Configuration:
(a) Power Supply Option: The kit includes a 5-V power supply input to power supply jack J17. For
proper EVM operation and to prevent damage to the EVM, only use a 5-V power supply.
(b) Analog Input Option: The on-board ADS62P49 has dual-channel transformer-coupled inputs from
J3 (Ch. A) and J6 (Ch. B).
(c) Clock Option: The on-board CDCE72010 provides a crystal-filtered LVCMOS clock at 245.76 MHz
to the on-board ADS62P49. The reference clock input of 19.2 MHz to the TSW4200-ADC is at J19.
The CDCE72010 is configured in PLL mode by default using the on-board 491.52-MHz VCXO. The
CDCE72010’s output has the divider configured to be divide-by-2, dividing the 491.52-MHz VCXO
clock to the required 245.76-MHz clock.
2. The EVM has the default jumper setting listed on Table 3 .
3. For more details, refer to the ADS62PXXEVM User’s Guide ( SLAU237 ).
4 TSW4200 Demonstration Kit SLWU071C – April 2010 – Revised November 2012
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