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Software Operation
Figure 4. Default CDCM7005 SPI GUI
The divider parameters, M and N, are determined according to the following equation based on the
internal reference frequency and internal VCXO frequency.
F
REF
= (F
VCXO
×
M)/(N
×
P)
The p parameter is the VCXO input divider and set through the FB_MUX value. The M and N counter
values need to be adjusted depending on the board configuration. The M and N counter registers are
determined by the reference frequency and the VCXO frequency. The OUT_MUX sets the divide ratios for
the individual output clocks. The OUTSEL determines whether the output clocks will be used as
single-ended CMOS or differential LVPECL. With a 10-MHz reference oscillator the CDCM7005 settings
are shown in
for a variety of common VCXO frequencies. For other frequencies, see to the
CDCM7005 data sheet for more details.
Table 2. CDCM7005 Register Values
VCXO Freq. (MHz)
491.52
245.76
122.88
61.44
Divider M
125
125
125
125
Divider N
768
768
768
768
FB_MUX
8
4
2
1
SLWU013A – March 2004 – Revised September 2005
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