Texas Instruments TSW14J58 JESD204C, User Manual, Page: 8 / 23

3.3 LEDs
3.3.1 Power and Configuration LEDs
Several LEDs are on the TSW14J58 EVM to indicate the presence of power and the state of the FPGA. The
description of these LEDs is found in
Table 3-3 .
Table 3-3. Power and Configuration LED Description of the TSW14J58 Device
Component Description
D4 On if USB2.0 device is powered up
DS4 USB3.0 FT601 device wakeup
DS5 On if USB3.0 cable is connected between EVM and host PC
D16 On if firmware has been loaded into FPGA
D17 On after power up and after firmware has been loaded
DS20 On if 5.5 V is present and power switch is turned on
TXSYNC On when EVM powers up
RXSYNC Not used
TX Active Not used
RX Active On when EVM powers up. Off when firmware is loaded
GT_Pwr Good On when EVM powers up. Off when firmware is loaded
SYSREFT Done Not used
DDR Calib On when EVM powers up and when firmware is loaded
PLL Lock On when EVM powers up and when firmware is loaded
3.3.2 Spare LEDs
The TSW14J58EVM has five spare LEDs on the TSW14J58EVM. These are disabled by default.
DS2 – SYNCA
D2S3 – SYNCB
DS6 – TRIG_IN
DS7 – CAL TRIG
DS8 – CAL STAT
To enable the LEDs, place the shunt on J34 to pin 2–3.
3.3.3 Connectors
3.3.3.1 SMA Connectors
The TSW14J58 has 5 SMA connectors. Table 3-4 defines the connectors:
Table 3-4. SMA Connectors
Component Connector Description
J12 REFCLKP1 Spare external FPGA reference clock+. Must install C527 and remove C552 to use this input. This
connects to FPGA clock input ball H7
J13 REFCLKN1 Spare external FPGA reference clock–. Must install C528 and remove C553 to use this input. This
connects to FPGA clock input ball H6
J31 SYNCA 3V3 CMOS logic SYNC output. J21 must have shunt installed between pins 1–2 to enable this
output. This signal is sourced by FPGA ball J15. A shunt on pins 2–3 of J34 enables SYNCA LED.
J32 SYNCB 3V3 CMOS logic SYNC output. J21 must have shunt installed between pins 1–2 to enable this
output. This signal is sourced by FPGA ball G14. A shunt on pins 2–3 of J34 enables SYNCB LED.
J36 SYNCC 3V3 CMOS logic SYNC output. J21 must have shunt installed between pins 1–2 to enable this
output. This signal is sourced by FPGA ball G19.
J33 TRIG IN 3V3 CMOS logic trigger input to FPGA pin G12. A shunt on pins 2–3 of J34 enables TRIG IN LED.
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