Texas Instruments TSW14J57EVM, User Manual

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+12 VDC
Input
Power Sequencer/
Monitor
16Gb DDR4
RAM
LDO and Switch
Regulators
Intel
®
Arria
®
10 FPGA
(Firmware)
USB
to
Parallel
USB 3.0
Port
FMC+ Connector
ADC or DAC EVM
TSW14J57 EVM
Copyright © 2017, Texas Instruments Incorporated
32 Bit 100 MHz
Parallel Interface
JESD204B Interface
Data, Device, CLK,
SYSREF, SYNC, GPIO
Functionality
www.ti.com
4 SLWU092 – April 2017
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Copyright © 2017, Texas Instruments Incorporated
TSW14J57 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
• Supported by TI HSDC PRO software
• FPGA firmware developed with Quartus
®
Prime 16.1 and QSYS
– JESD RX IP core with support for:
• USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA configuration data accessible through USB and JTAG
• Lane alignment and character replacement enabled or disabled through USB and JTAG
– JESD TX IP core with support for:
• USB and JTAG reconfigurable JESD core parameters: L, M, K, F, HD, S, and more
• ILA data configured through USB and JTAG
• Character replacement enabled or disabled through USB and JTAG
– Dynamically reconfigurable transceiver data rate. Operating range from 2 to 15 Gbps
Figure 2 shows a block diagram of the TSW14J57 EVM.
Figure 2. TSW14J57 EVM Block Diagram