Texas Instruments TSW14J57EVM, User Manual

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Introduction
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2 SLWU092 – April 2017
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Copyright © 2017, Texas Instruments Incorporated
TSW14J57 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
Trademarks
Intel, Arria are registered trademarks of Intel.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
All other trademarks are the property of their respective owners.
1 Introduction
The TI TSW14J57 evaluation module (EVM) is a next generation pattern generator and data capture card
used to evaluate performances of the new TI JESD204B device family of high-speed analog-to-digital
converters (ADC) and digital-to-analog converters (DAC). For an ADC, by capturing the sampled data over
a JESD204B interface when using a high-quality, low-jitter clock, and a high-quality input frequency, the
TSW14J57 can be used to demonstrate datasheet performance specifications. Using Intel
®
PSG
JESD204B IP cores, the TSW14J57 can be dynamically configurable to support lane speeds from 2 Gbps
to 15 Gbps, from 1 to 16 lanes with one firmware build. Together with the accompanying
High-Speed Data
Converter Pro Graphic User Interface (GUI), it is a complete system that captures and evaluates data
samples from ADC EVMs and generates and sends desired test patterns to DAC EVMs.
2 Functionality
The TSW14J57EVM has a single industry standard FMC+ connector that interfaces directly with TI
JESD204B ADC and DAC EVMs. The FMC+ carrier connector is compatible with the FMC mezzanine
connector. When used with an ADC EVM, high-speed serial data is captured, de-serialized and formatted
by an Intel
®
Arria
®
10 FPGA. The data is then stored into an external DDR4 memory bank, enabling the
TSW14J57 to store up to 1G 16-bit data samples. To acquire data on a host PC, the FPGA reads the data
from memory and transmits it on a high speed 16 bit parallel interface. An onboard high-speed USB 3.0 to
parallel converter bridges the FPGA interface to the host PC and GUI.
In pattern generator mode, the TSW14J57 generates desired test patterns for DAC EVMs under test.
These patterns are sent from the host PC over the USB interface to the TSW14J57. The FPGA stores the
data received into the board DDR4 memory module. The data from memory is then read by the FPGA and
transmitted to a DAC EVM across the JESD204B interface connector. The board contains a 100-MHz
oscillator used to generate the DDR4 reference clock and a option for a 10-MHz oscillator for general-
purpose use.
Figure 1 shows the TI TSW14J57 evaluation module.