Copyright © 2017, Texas Instruments Incorporated
Functionality
3
SLWU092 – April 2017
Copyright © 2017, Texas Instruments Incorporated
TSW14J57 JESD204B High-Speed Data Capture and Pattern Generator
Card User's Guide
Figure 1. TSW14J57EVM
The major features of the TSW14J57 are:
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Subclasses: 0 (backward compatible), 1, 2
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Support for deterministic latency
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Serial lanes speeds up to 15 Gbps
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16 routed transceiver channels
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16Gb DDR4 SDRAM (split into four independent 256×16, 4Gb SDRAMs). Quarter rate DDR4
controllers supporting up to 1200-MHz operation
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1G of 16-bit samples of onboard memory
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Supports 1.8- and 2.5-V CMOS IO standard
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General purpose 100-MHz oscillator
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Onboard UCD90120A for power sequencing and monitoring
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Onboard Cypress CYUSB301X USB 3.0 device for JTAG and parallel interface to the FPGA
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Reference clocking for transceivers available through FMC+ port or SMAs
