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TI TSW1405 High-Speed ADC Evaluation Board
HDL User’s Guide
Table 9. Single Channel Edge Bit-Wise Design Signal Names and Pinout
Hardware Validation
Hardware was validated using the ADS61B49EVM, ADS4249, ADS58C48, ADS5400, ADS5463, ADS5485,
TSW1405, two function generators and a DC power supply. The FPGA firmware was synthesized and programed
using Lattice Diamond
®
1.4 design software. ADC results were analyzed through the Texas Instruments High-
Speed Data Converter Pro 1.0/1.04 GUI. The input clock frequency was set to 15 MHz at 1.5 Vpp and the ADC
input was set to 100 kHz at 4.5Vpp. The supply to the ADC board was 5V or 6V depending on the board.
Signal Name
LatticeECP3 Pin
Direction
Definition
reset_n
C21
Input
Master Reset
clk_lvds_rx_p
L4
Input
Clock from TI ADC
clk_lvds_rx_n
M4
Input
TI ADC Channel 1 Data
lvds_rx_port0_p[4]
AA1
lvds_rx_port0_n[4]
Y2
lvds_rx_port0_p[5]
T4
lvds_rx_port0_n[5]
T5
lvds_rx_port0_p[6]
U1
lvds_rx_port0_n[6]
U2
lvds_rx_port0_p[7]
N3
lvds_rx_port0_n[7]
P3
lvds_rx_port0_p[9]
L3
lvds_rx_port0_n[9]
L2
lvds_rx_port0_p[10]
N4
lvds_rx_port0_n[10]
P4
lvds_rx_port0_p[11]
N5
lvds_rx_port0_n[11]
P6
lvds_rx_port0_p[12]
R7
lvds_rx_port0_n[12]
T7
clk_spi
A20
Input
SPI Clock
spi_miso
B19
Output
SPI Data Out
spi_ss
B20
Input
SPI Source Select
LED
F19
Output
ADC Clock Active Status
regbit
G18
Output
Reserved