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1
rd1127_01.2
May 2012
Reference Design RD1127
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
The TSW1405EVM Low Cost Data Capture Card from Texas Instruments (TI) assists designers in prototyping and
evaluating the performance of high-speed ADCs that feature parallel/serial LVDS outputs. The evaluation module
features a powerful LatticeECP3™-35 FPGA. The FPGA can be used as a flexible and rapid prototyping environ-
ment for digital design, interfacing directly to the LVDS output of the TI ADC under evaluation. This HDL reference
design is available for users to get started with the evaluation board and capture ADC data using the TI High Speed
Data Converter Pro software.
Figure 1. Hardware Evaluation Overview
Currently, HDL reference designs targeting the LatticeECP3 device support the following TI device families:
• ADS41xx and ADS61xx single channel
• ADS62Pxx and ADS42xx dual channel
• ADS58C48 four channel
• ADS5400 dual bus
• ADS5463 single channel
• ADS5485 single channel
The HDL reference designs for these converters contain two primary modules for capturing the LVDS data from the
ADC.
•
ADCIF
– Contains the I/O logic and gearing functions for the LVDS pins. It also converts the double data rate
(DDR) input channel to a single data rate (SDR) parallel bus.
•
DUMPMEM_TOP
– Stores the channel’s parallel data to internal DPRAM. The ADC data extracts a SPI control-
ler within the module. The High Speed Data Converter Pro software can import the data from this controller
through the USB port.
ADCIF module is the only design block required if the user desires to implement their own design using the
ADS41xx/ADS61xx, ADS62Pxx/ADS42xx, ADS58C48, ADS5400, ADS5463, ADS5485 with the LatticeECP3
device. The top level design instantiates the primary modules and connects them together. It also contains a LED
blinker circuit. This circuit flashes the LED when the LVDS clock output from the ADC is running and is available to
the FPGA. Figures 2 to 7 show the block diagrams for each respective ADC design.
ADS EVM
TSW1405
High Speed Data Converter Pro
TI TSW1405 High-Speed ADC
Evaluation Board
HDL User’s Guide
