Texas Instruments TSW12QJ1600, User Manual

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15 SLAU796 – July 2020
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Copyright © 2020, Texas Instruments Incorporated
Device Configuration
Chapter 4
SLAU796 – July 2020
Device Configuration
The ADC device is programmable through the serial programming interface (SPI) bus accessible through
the FTDI USB-to-SPI converter located on the EVM. A GUI is provided to write instructions on the bus and
program the registers of the ADC device.
4.1 Supported JESD204C Device Features
The ADC device supports some configuration of the JESD204C interface. Due to limitations in the
TSW14J58EVM firmware, all JESD204C link features of the ADC device are not supported.
Table 4-1 lists
the supported and non-supported features.
(1)
Dependent on bypass or decimation mode and output rate selection. Always disable the JESD204 block before changing any of
the JESD204C settings. Once the settings are changed, re-enable the JESD204 block.
Table 4-1. Supported and Non-Supported Features of the JESD204C Device
JESD204C Feature Supported by ADC Device Supported by TSW14J58EVM
Number of lanes per link (L) L = 2, 3, 4, 6, 8
(1)
L = 1, 2, 3, 4, 6, 8 supported
Total number of lanes active 2,,3 4, 6, 8 2, 4, 6, 8, 12, 16
Number of frames per multiframe (K)
K
min
= 4–256,
(1)
K
max
= 256, K
step
= 4, 16 or 32
Most values of K supported, constrained by
requirement that
K × F = 4
n
Scrambling Supported Supported
Encoding 8B/10B and 64B/66B 8B/10B
Test patterns
PRBS7, PRBS9, PRBS15, PBRS23, PRBS31, Ramp,
Transport Layer test, D21.5, K28.5, Repeat ILA,
Modified RPAT, Serial Out 0, Serial Out 1, Clock test,
ADC Test Pattern
(1)
ILA, Ramp, Long/Short Transport
Speed Lane rates from 0.8 to 17.16 Gbps
(1)
Lane rates from 12 to 16 Gbps
ƒ
(SAMPLE)
parameter must be properly set in HSDC
Pro GUI.
4.2 Tab Organization
Control of the ADC1 and ADC2 device features are available in the EVM, ADC PLL, Control and
JESD204C tabs for respective ADCs.