2.6.5
Clock and Digital Signal Routing
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EVM + PC
The TSC2117 has a flexible and complex clock and digital signal routing architecture.
Two processors can connect to the TSC2117 using two separate I2S™ interfaces: The primary I2S
interface has dedicated pins whereas the secondary I2S interface signals can be assigned to a selection
of pins.
The TSC2117 has an on-chip clock generation module which can be configured to generate the sampling
rate, modulator clocks, converter clocks, bit clock and word clock.
Click on the “Digital Audio Processing Serial Interface” active object (if it is not within the current scope of
the main window, drag the block diagram to the left until the active object appears). This will change the
block diagram to the clock and digital signal routing diagram:
Figure 6. Clock and Digital Signal Routing
The clock and digital signal routing diagram shows the current state of the TSC2117 routing configuration
and allows interactive manipulation.
•
Each clock or signal source has its own unique color. For example, the BCLK signal from the internal
clock generation module has a turquoise color.
•
To trace the routing of a specific signal, follow its color. The example in
Figure 6
shows that the BCLK
signal from the internal clock generation module is routed to the primary I2C™ BCLK pin (which is
configured as an output), to the secondary I2S BCLK signal (which is not connected to a pin) and to
the BCLK input of the codec (ADC and DAC within the TSC2117).
•
To change the definition of a pin (input or output), click the active object (arrow) that belongs to the pin.
Only pins that can change between input and output are linked to such an active object. The clock
routing diagram will automatically change to reflect the new routing.
•
Some of the switches within the diagram are active objects, which can be manipulated using the
mouse pointer. Other switches open or close depending on the state of the associated pin.
•
To assign a pin to a signal of the secondary I2S interface, choose one of the available pins in the drop
down box that belongs to the signal. The list of available pins will change automatically depending on
the assignment of other signals to pins.
•
Click on the “Back To Codec” active object to return to the previous block diagram.
•
Click on the “Internal Clock Gen Module” active object to display the digital configuration dialog.
SLAU282 – April 2009
TSC2117EVM-K
11
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