Texas Instruments TPS92682EVM, User Manual, Page: 41 / 49

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TPS92682EVM-70 Power UP and Operation
41 SLUUC13A – May 2019 – Revised August 2019
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TPS92682EVM Constant Current Two-channel Boost and Boost-to-Battery
Figure 51. Devices Window Setting
After applying these settings, the fault status registers FLT1 (0x11) and FLT2 (0x12) must be checked.
Before enabling and turning on the outputs, the fault registers must be read (cleared). The Power Cycle
(PC) bit must be cleared in order for the TPS92682-Q1 is enabled. The fault status can be obtained by
pushing the
Read Faults button in Figure 52 .
Figure 52. Fault Status after Pushing the Read Faults Once
The first time the Read Fault button is pushed, the previous status of the fault registers are shown and the
faults are cleared. The second time the Read Faults button is pushed, the cleared faults will change to
green as shown in
Figure 53 .
Figure 53. Fault Status after Pushing the Read Faults Twice