Texas Instruments TPS7A53EVM-080 User Manual Download Page 10

4 TPS7A53EVM-080 Schematic

Figure 4-1

 shows a schematic for the TPS7A53EVM-080.

GND

1.00k

R15

1

2

3

J8

GND

J3

J4

J15

J14

1

2

J9

IN

Vin Recommended Max = 6V

Vout Max = 3.6V

Iout Max = 3A

1nF
100V

C21

VDD

A1

OUTH

A2

OUTL

B2

IN-

C2

GND

B1

IN+

C1

LMG1020YFFR

U2

1

M

N

T

_

1

M

N

T

_

2

M

N

T

_

3

M

N

T

_

4

J22

J19

VDD

J26

GND

50V
10uF

C20

50V
10uF

C19

1.00k

R7

1
2

J16

50V
0.1uF

C18

154

R11

154

R12

154

R10

154

R9

EN

154

R8

100V
1pF

C16

0

R17

0

R13

3

5

,6

,8

4

,7

1

,2

,

Q1
CSD17313Q2

1nF
100V

C22

0

R18

J18

49.9

R20

GND

J24

1

2

J10

25V
1000pF

C1

10µF
10V

C12

FB

BIAS

FB

J5

J13

BIAS Recommended Max = 6V

VDD Recommended Max = 5.4V

VDD

25V
10uF

C2

1.00

R3

25V
10uF

C17

1.00

R19

25V
10uF

C7

1.00

R2

J11

J12

J25

20k

R16

20k

R14

J20

1

2

3

4

J7

1

2

3

4

J6

GND

GND

BIAS

OUT

SS

13.3k

R6

OUT

TP5

10V

1uF

C8

10V
0.01uF

C9

0

R1

0

R4

1

M

N

T

_

1

M

N

T

_

2

M

N

T

_

3

M

N

T

_

4

J23

1

MNT_ 1

MNT_ 2

MNT_ 3

MNT_ 4

J21

1

M

N

T

_

1

M

N

T

_

2

M

N

T

_

3

M

N

T

_

4

J1

GND

1

M

N

T

_

1

M

N

T

_

2

M

N

T

_

3

M

N

T

_

4

J2

GND

+

330uF
16V

C15

10µF
10V

C11

10µF
10V

C13

10µF
10V

C14

47µF
6.3V

C10

10µF
10V

C5

+

330uF
16V

C6

10µF
10V

C4

10µF
10V

C3

TP1

TP4

TP2

TP6

TPS7A5310AQWRTJRQ1

OUT

1

OUT

19

OUT

20

I N

15

I N

16

I N

17

BI AS

12

EN

14

NC

3

NR/ SS

13

PG

4

Thermal_ Pad

21

SNS

2

NC

5

NC

6

NC

7

NC

9

NC

10

NC

11

GND

8

GND

18

U1

0

R5

TP3

FB

2

4

6

8

10

12

14

16

18

20

J17B

1

3

5

7

9

11

13

15

17

19

J17A

OUT

NC

NC

NC

NC

SS

IN

IN

OUT

SNS

PG

GND

NC

NC

BIAS

EN

IN

GND

OUT

NC

SNS

GND

PG

Figure 4-1. Schematic

TPS7A53EVM-080 Schematic

www.ti.com

10

TPS7A53EVM-080 Evaluation Module

SBVU078 – NOVEMBER 2022

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Summary of Contents for TPS7A53EVM-080

Page 1: ...ow dropout linear regulator LDO Included in this user s guide are setup and operating instructions thermal and layout guidelines a printed circuit board PCB layout a schematic diagram and a bill of ma...

Page 2: ...sults 1 mA to 3 A Load Step 7 Figure 2 4 TPS7A53EVM 080 Load Transient Results 3 A to 1 mA Load Step 7 Figure 3 1 Top Assembly Layer and Silkscreen 8 Figure 3 2 Top Layer Routing 8 Figure 3 3 Layer 2...

Page 3: ...1 LDO Input Output Connector Descriptions 2 1 1 VIN and GND VIN and GND are the connection terminals for the input supply The VIN terminal is the positive connection and the GND terminal is the negat...

Page 4: ...ET drain to source voltage 2 2 4 J21 J21 is a high frequency kelvin connection that allows accurate measurements of the load transient MOSFET drain to source voltage 2 2 5 J22 J22 is the connection fo...

Page 5: ...installed on the EVM The TPS7A53A Q1 LDO can be enabled or disabled by using the J8 3 pin header Place a 2 pin shunt across the header to tie VIN to EN to enable the device Place a 2 pin shunt across...

Page 6: ...where damping can be installed include C2 and R3 C7 and R2 and C17 and R19 WARNING Current probe sensors can be tied to GND and must not come into contact with energized conductors See the user manua...

Page 7: ...12 Configure a function generator for the 50 output in a 0 V DC to 5 V DC square pulse If necessary burst mode can be configured in the function generator for repetitive low duty cycle load transient...

Page 8: ...2 are most at risk of raising the junction temperature during normal operation The LDO can become hot to the touch during normal operation see the thermal impedance discussion in the TPS7A53A Q1 data...

Page 9: ...5 Figure 3 7 Bottom Layer Routing Figure 3 8 Bottom Assembly Layer and Silkscreen www ti com Board Layout SBVU078 NOVEMBER 2022 Submit Document Feedback TPS7A53EVM 080 Evaluation Module 9 Copyright 2...

Page 10: ...k R16 20k R14 J20 1 2 3 4 J7 1 2 3 4 J6 GND GND BIAS OUT SS 13 3k R6 OUT TP5 10V 1uF C8 10V 0 01uF C9 0 R1 0 R4 1 MNT_1 MNT_2 MNT_3 MNT_4 J23 1 MNT_1 MNT_2 MNT_3 MNT_4 J21 1 MNT_1 MNT_2 MNT_3 MNT_4 J1...

Page 11: ...1 CONN HEADER VERT 20POS 2MM Header 2 54mm 10x2 TH NRPN102PAEN RC Any J22 J23 2 CONN SMA JACK STR 50 OHM PCB SMA Straight Jack TH RF2 04A T 00 50 G Adam Tech Q1 1 MOSFET N CH 30 V 5 A DQK0006C WSON 6...

Page 12: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 13: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 14: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 15: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 16: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 17: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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