Texas Instruments TPS7A53EVM-080 User Manual Download Page 6

If desired, a current probe can be inserted in the EVM as shown in 

Figure 2-2

 to measure the input and output 

current. The slots were sized to fit most current probes, such as the LeCroy

 AP015 or CP031 current probes.

Figure 2-2. TPS7A53EVM-080 With Current Probes Attached

The user has two options for providing a DC load on the output of the TPS7A53A-Q1. J10 can be used to place 
a DC load that flows through the current sense path on the output of the LDO. Alternatively, the J4 (VOUT) and 
J15 (GND) banana connectors can be used for external measurements and loading; however, the IOUT loop 
does not sense current flowing through these connectors. In cases where very fast transient tests are performed, 
ringing can occur on VIN or VOUT as a result of the PCB parasitic inductance. Placing a strip of wire on the 
exposed copper in the current path can reduce this ringing. 10 AWG wire can be used as needed. If ringing 
persists, install damping networks by adding a series resistor and capacitor in parallel with VIN. Locations where 
damping can be installed include C2 and R3, C7 and R2, and C17 and R19.

WARNING

Current probe sensors can be tied to GND and must not come into contact with energized 
conductors. See the user manual of your current probe for details. If your current probe has this 
limitation, use a thin strip of electrical or Kapton

®

 tape to isolate the current sense path from the 

current probe.

Optional kelvin sense points are provided using the SMA connectors J2 (VIN) and J1 (VOUT).

2.4 Optional Load Transient Circuit Operation

The TPS7A53EVM-080 evaluation module contains an optional high-performance load transient circuit to allow 
efficient testing of the TPS7A53A-Q1 LDO load transient performance. To use the optional load transient circuit, 
install the correct components in accordance with the application. Modify the input and output capacitance 
connected to the TPS7A53A-Q1 LDO to match the expected operating conditions. Determine the desired peak 
current to test, and modify the parallel resistor combination of R8, R9, R10, R11, and R12 as shown:

I

Peak

=

VOUT

R8 R9 R10 R11 R12

(1)

Setup

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TPS7A53EVM-080 Evaluation Module

SBVU078 – NOVEMBER 2022

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Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for TPS7A53EVM-080

Page 1: ...ow dropout linear regulator LDO Included in this user s guide are setup and operating instructions thermal and layout guidelines a printed circuit board PCB layout a schematic diagram and a bill of ma...

Page 2: ...sults 1 mA to 3 A Load Step 7 Figure 2 4 TPS7A53EVM 080 Load Transient Results 3 A to 1 mA Load Step 7 Figure 3 1 Top Assembly Layer and Silkscreen 8 Figure 3 2 Top Layer Routing 8 Figure 3 3 Layer 2...

Page 3: ...1 LDO Input Output Connector Descriptions 2 1 1 VIN and GND VIN and GND are the connection terminals for the input supply The VIN terminal is the positive connection and the GND terminal is the negat...

Page 4: ...ET drain to source voltage 2 2 4 J21 J21 is a high frequency kelvin connection that allows accurate measurements of the load transient MOSFET drain to source voltage 2 2 5 J22 J22 is the connection fo...

Page 5: ...installed on the EVM The TPS7A53A Q1 LDO can be enabled or disabled by using the J8 3 pin header Place a 2 pin shunt across the header to tie VIN to EN to enable the device Place a 2 pin shunt across...

Page 6: ...where damping can be installed include C2 and R3 C7 and R2 and C17 and R19 WARNING Current probe sensors can be tied to GND and must not come into contact with energized conductors See the user manua...

Page 7: ...12 Configure a function generator for the 50 output in a 0 V DC to 5 V DC square pulse If necessary burst mode can be configured in the function generator for repetitive low duty cycle load transient...

Page 8: ...2 are most at risk of raising the junction temperature during normal operation The LDO can become hot to the touch during normal operation see the thermal impedance discussion in the TPS7A53A Q1 data...

Page 9: ...5 Figure 3 7 Bottom Layer Routing Figure 3 8 Bottom Assembly Layer and Silkscreen www ti com Board Layout SBVU078 NOVEMBER 2022 Submit Document Feedback TPS7A53EVM 080 Evaluation Module 9 Copyright 2...

Page 10: ...k R16 20k R14 J20 1 2 3 4 J7 1 2 3 4 J6 GND GND BIAS OUT SS 13 3k R6 OUT TP5 10V 1uF C8 10V 0 01uF C9 0 R1 0 R4 1 MNT_1 MNT_2 MNT_3 MNT_4 J23 1 MNT_1 MNT_2 MNT_3 MNT_4 J21 1 MNT_1 MNT_2 MNT_3 MNT_4 J1...

Page 11: ...1 CONN HEADER VERT 20POS 2MM Header 2 54mm 10x2 TH NRPN102PAEN RC Any J22 J23 2 CONN SMA JACK STR 50 OHM PCB SMA Straight Jack TH RF2 04A T 00 50 G Adam Tech Q1 1 MOSFET N CH 30 V 5 A DQK0006C WSON 6...

Page 12: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 13: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 14: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 15: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 16: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 17: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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