External Capacitor Requirements – ESR
3-8
Figure 3–5. LDO Output Stage With Parasitic Resistances ESR and ESL
LDO
V
in
V
ESR
V
Cout
I
out
R
ESR
L
ESL
C
out
R
LOAD
V
out
In steady state (dc state condition) the load is supplied by the LDO (solid arrow)
and V
Cout
= V
out
. This means no current is flowing into the C
out
branch. If now
I
out
suddenly increases, the following occurs (see Figure 3–6 and the screen
shot in Chapter 4, Figure 4–7):
The LDO is not able to supply the sudden current need due to its response time
(t
1
in Figure 3–6). Therefore capacitor C
out
has to provide the current for the
new load condition (dashed arrow). C
out
acts like a battery now with an internal
resistance, ESR. Therefore, depending on the current demand at the output,
voltage drop will occur at R
ESR
and L
ESL
. This voltage is shown as V
ESR
in Fig-
ure 3–5. The internal inductance also causes an additional delay (shown as
t
L
in Figure 3–6), so C
out
could not immediately supply current to the load.
When C
out
is finally conducting current to the load, the initial voltage at the load
will be V
out
= V
Cout
– V
ESR
. Due to the discharge of C
out
, the output voltage V
out
will drop continuously until the response time t
1
of the LDO is reached and the
LDO will resume supplying the load. From this point the output voltage starts
rising again until it reaches the level directed by the LDO. This period is shown
as t
2
in Figure 3–6. The figure also shows the impact of different ESRs on the
output voltage. The left brackets show different levels of ESRs where number
1 displays the lowest and number 3 displays the highest ESR.
Understanding the above, one can draw the following conclusions:
-
The higher the ESR, the bigger the spike at the beginning of a load tran-
sient and the longer the time to return to a steady state.
-
The smaller the output capacitor, the faster the discharge time and the
bigger the voltage loss during the LDO response period (shown as t
1
in
Figure 3–6).
Conclusion:
The higher the output current and the load step differentials, the higher the
requirements for a C
out
with low ESR.
Summary of Contents for TPS76933
Page 15: ...Board Layout 1 9 Introduction Figure 1 5 Assembly Drawing top assembly...
Page 16: ...1 10...
Page 30: ...3 10...
Page 36: ...4 6...
