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LDO Linear Regulator Design

Using the Universal SOT23

EVM

August 1999

Mixed Signal Products

User’s Guide

SLVU019

Summary of Contents for TPS76933

Page 1: ...LDO Linear Regulator Design Using the Universal SOT23 EVM August 1999 Mixed Signal Products User s Guide SLVU019...

Page 2: ...ONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANT...

Page 3: ...contains the following chapters Chapter 1 Introduction Chapter 2 EVM Adjustments and Test Points Chapter 3 Circuit Design Chapter 4 Test Results Information About Cautions and Warnings This book may...

Page 4: ...or a warning is provided for your protection Please read each caution and warning carefully Related Documentation From Texas Instruments TPS760xx TPS761xx TPS763xx TPS764xx TPS769xx TPS770xx data she...

Page 5: ...Materials 1 6 1 5 Board Layout 1 8 2 EVM Adjustments and Test Points 2 1 2 1 Adjustment by Switch 2 2 2 2 Adjustment by Jumper 2 2 2 3 Adjustment by Trimmer 2 2 2 4 Adjustment by Programming Header 2...

Page 6: ...Influence to the Regulation of Vout at a Load Step From Low to High Output Current 3 9 4 1 Rise Time of Function Generator at Gate of MOSFET Q1 high speed 4 2 4 2 Rise Time of Function Generator at Ga...

Page 7: ...very low dropout voltage compared to standard LDOs makes the TPS76933 particularly suitable in battery applications requiring extended lifetime and low cost Low noise power supplies fast transient re...

Page 8: ...ws the circuit of a typical LDO application Figure 1 1 Typical LDO Application _ Control _ R1 R2 Q1 Vref LDO CO Vout Load _ VCC In the LDO application shown in Figure 1 1 the LDO regulates the output...

Page 9: ...ides a 3 3 V output voltage The maximum output current is 100 mA The 100 mA output power level is a reasonable selection criteria for powering DSPs and battery supplied applications such as mobile pho...

Page 10: ...Schematic 1 4 1 3 Schematic Figure1 2 shows the SLVP125 EVM Universal LDO Tester 3 3 V output with TPS76933 as U1 schematic diagram Figure 1 2 SLVP125 EVM Universal LDO Tester Schematic Diagram...

Page 11: ...Schematic 1 5 Introduction Figure 1 2 SLVP125 EVM Universal LDO Tester Schematic Diagram Continued...

Page 12: ...minal block 3 pin 6 A 3 5 mm OST 3 5mm JP1 PTC36SAAN Header single row straight 2 pin 0 100 x 25 mil Sullins 0 1 JP2 PTC36SAAN Header single row straight 2 pin 0 100 x 25 mil Sullins 0 1 JP3 PTC36SAAN...

Page 13: ...06 2512 R30 Std Resistor chip 10 0 M 1 8 W 1 1206 R31 Std Resistor chip 10 K 1 8 W 5 1206 R32 72 T93YA 50K Trim pot cermet 50 K vertical top adjust 1 2 W 10 Vishay 3x 0 1 S1 EG1218 Switch 1P2T slide P...

Page 14: ...Board Layout 1 8 1 5 Board Layout Figures 1 3 through 1 6 show the board layout for the SLVP125 EVM Figure 1 3 Top Layer Figure 1 4 Bottom Layer top view...

Page 15: ...Board Layout 1 9 Introduction Figure 1 5 Assembly Drawing top assembly...

Page 16: ...1 10...

Page 17: ...justment by switch Adjustment by jumper Adjustment by trimmer Adjustment by programming header Figure 2 1 shows the locations of the adjustment points on the board Topic Page 2 1 Adjustment by Switch...

Page 18: ...ns Function Device DUT1 DUT2 Bypasses input resistor JP1 JP10 Enables DUT JP2 JP7 Bypasses ESR emulation JP3 JP8 Set minimum load JP4 JP9 Set maximum load JP5 JP11 Toggles between input voltage direct...

Page 19: ...oltage transient impact Input voltage transient impact 2 5 Test Setup Figure 2 2 shows the test setup Follow these steps for initial power up of the SLVP125 1 Populate the test devices on the board U1...

Page 20: ...put voltage up to the desired maximum but not further than 13 5 V 5 Verifythattheoutputvoltage measuredattheVout1andVout2pinsrespec tively has the desired value Note 1 With very small loads 100 A you...

Page 21: ...uit Design This chapter describes the LDO circuit design procedure Topic Page 3 1 Adjusting the TPS76xx01 TPS77001 Output Voltage 3 2 3 2 Temperature Considerations 3 6 3 3 External Capacitor Requirem...

Page 22: ...n and the input pin Note All TPS76x01 TPS77001 devices except the TPS764xx use pin 4 as a feed back pin for the adjustable version At the TPS764xx pin 4 acts as a bypass pin for an external bypass cap...

Page 23: ...or ratio R1 R2 Table 3 1 Exact Resistor Values Vout R1 R2 Maximum Value for R1 R2 k 1 2 0 018676 171 429 1 3 0 103565 185 714 1 4 0 188455 200 000 1 5 0 273345 214 286 1 6 0 358234 228 571 1 7 0 44312...

Page 24: ...593 700 000 5 3 244482 714 286 5 5 3 66893 785 714 6 4 093379 857 143 6 5 4 517827 928 571 7 4 942275 1000 000 7 5 5 366723 1071 429 8 5 791171 1142 857 8 5 6 21562 1214 286 9 6 640068 1285 714 9 5 7...

Page 25: ...s is 261 kW 169 kW 1 544379 Error 1 1 544379 1 546689 100 0 149371 A free ware program called WinResis available on the Internet can help you find the correct resistor values Table 3 2 E96 Resistor Se...

Page 26: ...or equal to PD max The maximum power dissipation limit is determined using the following equation PD max TJ max TA RqJA Where TJ max is the maximum allowed junction temperature C i e 125 C for the TP...

Page 27: ...capacitance every capacitor also contains parasatic resistances These parasatic resistances are ohmic resistances as well as inductive impedances The ohmic resistances are called equivalent series res...

Page 28: ...ely supply current to the load When Cout is finally conducting current to the load the initial voltage at the load willbeVout VCout VESR DuetothedischargeofCout theoutputvoltageVout will drop continuo...

Page 29: ...w to High Output Current ESR 1 ESR 2 ESR 3 3 1 2 tL t1 t2 Iout Vout In order to get a good performing system an LDO with short response time and an output capacitor with low ESR are required For any r...

Page 30: ...3 10...

Page 31: ...4 1 Test Results Test Results This chapter presents laboratory test results for the LDO design Topic Page 4 1 Test Results 4 2 Chapter 4...

Page 32: ...gh 4 7 show the results of various tests and test conditions for the circuit using the TPS76933 device Figure 4 1 Rise Time of Function Generator at Gate of MOSFET Q1 high speed Figure 4 2 Rise Time o...

Page 33: ...st Results 4 3 Test Results Figure 4 3 Transient at Input Ch1 4 3 V Input 3 3 V Output Ch2 at 100 mA Load Cout 10 F Spike Output Voltage Figure 4 4 Delay Time EN Output High Enable Pulse Output Voltag...

Page 34: ...l Load 100 mA No Load Transition Vout Whole Period Load Transition Output Voltage see Note 2 see Note 1 Figure 4 6 Full Load 100 mA No Load Transition With Cout 10 F Electrolytic Load Transition Outpu...

Page 35: ...easured as the voltage drop at the drain of Q1 see Figure 1 2 Therefore load on is displayed as 0 V and load off is displayed as 3 3 V 2 In order to display the output voltage transient with high reso...

Page 36: ...4 6...

Page 37: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments TPS76XXXEVM 125...

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