Test Setup
3-4
Testing
Figure 3–2. Quiescent Current vs Output Current
1
1.2
1.4
1.6
1.8
2
0
20
40
60
80
100
QUIESCIENT CURRENT
vs
OUTPUT CURRENT
VADJ = 1 V
VIN = 5 V
IO – Output Current – mA
– Quiscent Current – mA
I Q
Figure 3–3. Line Regulation
1.02
1.025
1.03
1.035
1.04
1.045
1.05
2
3
4
5
6
7
8
9
10
II=99.4 mA
II=15 mA
VI – Input Voltage – V
– Output V
oltage – V
V
O
LINE REGULATION
Summary of Contents for TPS769 Series
Page 4: ...iv...
Page 6: ...vi...
Page 12: ...1 6 Introduction...
Page 16: ...Board Layers 2 4 Board Layers and Assembly Drawings Figure 2 5 Drill Drawing and Drill Table...
Page 18: ...2 6 Board Layers and Assembly Drawings...
Page 24: ...3 6 Testing...