Texas Instruments TPS65986, User Manual

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1
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3
4
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5
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D D
C C
B B
A A
3 4
P owe r Path Sup plies
6 /19/2 015
HVL 117 D_ Pow er_ Path.Sch Do c
She et Title :
S ize:
Mod. Da te:
Fi le:
She et: of
B h ttp ://ww w.ti.co m
Con tact: j-o ntive ros@ ti .co m
TPS65 98 2EVM Proje ct Title:
Des ign ed fo r: Pu bl ic Re lea se
Assemb ly Va rian t: -0 01
© Tex as Ins trument s 2015
Dra wn By:
Eng in ee r:
Jaco b O ntive ros
Te xas I nstrume nts an d/or its li cen sors do not wa rran t the accur acy or co mpl eten ess of th is sp ecifi cation or an y inform ation con ta in ed the rei n. Te xas I nstrume nts an d/or its li cen sors do not
w arra nt th at th is de sig n wi ll mee t the spe cifica ti ons, wi ll be suita ble fo r yo ur a ppl ica ti on or fit f or an y particu la r purp ose , or will o pe rate in an i mple men tation . Te x as I nstrume nts an d/or its
l ice nso rs do no t warra nt th at th e de sig n is pro du ction worth y. You sho ul d comp le te ly valida te an d t est yo ur d esi gn im ple men tation to confir m the system f uncti ona li ty f or you r app li catio n. N ot in versi on contro l SVN Re v:
H VL11 7 Nu mbe r: R ev: D
VI N
1
VS E NSE
6
EN
8
RT
10
G ND
3
COM P
7
P H
2
B OOT
9
P AD
11
G ND
4
GND
5
U5
TPS54 335 D RCR
0 .1µF
C 26
0.1µF
C2 0
100k
R82
0 .1µF
C 23
DN P
C2 7 DN P
DNP
C3 0
D NP
DNP
R8 1
D NP
DNP
R8 3
D NP
G ND
GND
GND
GND
GND
GND
0 .1µF
C 37
0.1µF
C3 1
100k
R92
19.1k
R 94
0 .1µF
C 34
DN P
C3 8 DN P
DNP
C4 1
D NP
DNP
R9 3
D NP
G ND
GND
GND
GND
GND
GND
0 .1µF
C 48
0.1µF
C4 2
100k
R102
0 .1µF
C 45
DN P
C4 9 DN P
DNP
C5 2
D NP
DNP
R1 01
D NP
DNP
R1 03
D NP
G ND
GND
GND
GND
GND
GND
22µF
C 46
22µF
C47
G ND
VI N
1
VS E NSE
6
EN
8
RT
10
G ND
3
COM P
7
P H
2
B OOT
9
P AD
11
G ND
4
GND
5
U6
TPS54 335 D RCR
G ND
VI N
1
VS E NSE
6
EN
8
RT
10
G ND
3
COM P
7
P H
2
B OOT
9
P AD
11
G ND
4
GND
5
U7
TPS54 335 D RCR
G ND
22µF
C 35
22µF
C36
22µF
C24
22µF
C25
S y st em _3V 3
S y st em _5V
HV _S ource
1
2
3
J5
DNP
32.4k
R 84
7 .1 5k
R 104
S ENS E
1
GND
4
P OWE R
2
P OWE R
3
GND
5
S HIE LD
6
SHIELD
7
SHIELD
8
SHIELD
9
J4
JPD 113 5 -50 9-7 F
E xt ernal Po wer
G ND
TP5
S3
1 .00k
R 27
Sy s tem _RE S ET
Tiv a_5V S y st em _5V
Tiv a_3V 3 S y st em _3V 3
1 2
3 4
J7
DNP
10µF
C 33
10µF
C22
10µF
C44
DNP
R9 1
D NP
J9
47.5k
R 97
47.5k
R 10 9
8 .45k
R 95
100pF
C39
2200pF
C40
9 .53k
R 10 8
91pF
C50
1800pF
C51
330pF
C28
5600pF
C29
2 .74k
R 85
47.5k
R 88
Sy s te m_3V 3
Sy s te m_5V
Ex t ernal Power
External Power
External Power
S ys t em _3V3
HV_S ourc e
12V _V S ENS E
12V_VSENSE
5V _V S ENS E
5V_VSENSE
3V 3_V S ENS E
3V3_VSENSE
G ND
10uH
L4
10uH
L3
10uH
L2
Schematic
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The circuit diagram in Figure 4 shows the schematic for page 2 of the TPS65982-EVM. Page 2 includes power path-related ICs: the
External_Power to System_3V3 buck converter (U5) and passive components, the External_Power to System_5V buck converter (U6) and passive
components, the External_Power to HV_Source buck converter (U7) and passive components, the Barrel Jack receptacle (J4), the power rail
header (J5), the Tiva to System power jumper (J7), and the System_RESET push-button (S3).
Figure 4. TPS65982-EVM Schematic Page 2
30 TPS65982 Evaluation Module SLVUAF8C – June 2015 – Revised November 2015
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